Precharge circuit for enhancement mode memory circuits

Details Precharge circuit for enhancement mode memory circuits Precharge circuit for enhancement mode memory circuits

1984-08-13

1986-10-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307481, 307482, 307579, 307269, 307594, 307606, H03K 1706, H03K 19096

Patent

active

046187863

ABSTRACT:
A circuit for precharging the gates of pass transistor that will be subsequently bootstrapped employs a precharge circuit that generates a precharge pulse having magnitude greater than Vcc and distributes the pulse to a number of gate control circuits that raise the pass transistor gate voltages from a quiescent voltage level of Vcc-Vt to Vcc at a time before the bootstrapping signals arrive at the pass transistor.

REFERENCES:
patent: 3866061 (1975-02-01), Wen et al.
patent: 4289973 (1981-09-01), Eaton, Jr.
patent: 4360901 (1982-11-01), Proebsting
patent: 4401904 (1983-08-01), White, Jr. et al.
patent: 4521701 (1985-06-01), Reddy
patent: 4550264 (1985-10-01), Takahaski et al.
Hultman, "Memory Clock Design", IBM T.D.B., vol. 9, No. 10, Mar. 1967, pp. 1328-1329.

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