Electricity: measuring and testing – Magnetic – Magnetometers
Reexamination Certificate
1999-05-04
2001-04-10
Patidar, Jay (Department: 2862)
Electricity: measuring and testing
Magnetic
Magnetometers
C360S067000
Reexamination Certificate
active
06215302
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to preamplifiers for resistive transducers (such as a magneto-resistive transducers), and to methods for measuring the resistance of a resistive transducer. In preferred embodiments, the inventive preamplifier includes circuitry for measuring resistance of a resistive transducer (as well as potential difference across the transducer) during normal transducer operation.
BACKGROUND OF THE INVENTION
When positioned in an external magnetic field, the resistance of a magneto-resistive transducer varies in response to variations of the magnetic field over time. Magneto-resistive transducers have been used as read heads in magnetic disk drives and are being more commonly used for this purpose.
A typical magneto-resistive transducer includes a strip of nickel-iron metallization on a silicon substrate. A preamplifier coupled to the strip applies a bias voltage across the strip (to cause current flow through the strip), and while doing so generates an amplified signal indicative of the potential difference across the strip. The amplified signal then undergoes further processing.
A typical preamplifier of this type is shown in
FIG. 1A
, and a portion of the
FIG. 1A
circuit is shown in FIG.
1
. In
FIG. 1
, the magneto-resistive transducer is represented as a resistor having resistance R
MR
. The drain of PMOS transistor M
1
is coupled to one end of the transducer, the source of M
1
is coupled to the top rail (at potential V
CC
), the drain of NMOS transistor M
2
is coupled to the other end of the transducer, and the source of M
2
is coupled to the bottom rail (at potential V
EE
). The transducer is biased by asserting bias potentials V
BP
and V
BN
to the gates of transistors M
1
and M
2
, thereby applying a bias potential across the transducer and causing current I
MR
to flow through the transducer (and through transistors M
1
and M
2
). The magnitudes of the bias potentials V
BP
and V
BN
are chosen as a function of the transducer resistance (e.g., the transducer resistance in the presence of no magnetic field) and other factors to optimize system performance.
The potential difference (V
MR
) across the transducer is amplified to generate differential output OUT
P
, OUT
N
(indicative of the potential difference across the transducer), by an amplifier comprising NPN bipolar transistors Q
P1
and Q
P2
(whose bases are coupled to opposite ends of the transducer), NPN bipolar transistors Q
P3
and Q
P4
(whose bases are coupled to receive bias voltages VB
3
and VB
4
), current source
3
coupled to the common emitters of transistors Q
P1
and Q
P3
, and current source
4
coupled to the common emitters of transistors Q
P2
and Q
P4
. The output signal OUT
P
, OUT
N
is produced at the collectors of transistors Q
P1
and Q
P2
.
With reference to
FIG. 1A
, we next describe typical circuitry for producing the above-mentioned bias potentials V
BP
, V
BN
, V
B3
, and V
B4
which are employed in FIG.
1
.
In
FIG. 1A
, circuit
40
(which includes above-discussed transistor M
1
) is a current source which is biased, by potential V
SETP
asserted at the output of digital-to-analog converter
61
, to function as the source of the current I
MR
which flows through transducer R
MR
.
Op amp
62
, NPN bipolar transistor Q
62
, and resistor R
REF
(connected as shown in
FIG. 1A
) provide reference current I
REF
to digital-to-analog converter (“DAC”)
61
, when reference potential V
REF
is asserted at the noninverting input of op amp
62
. To control the output of DAC
61
, control logic
60
asserts control bits to DAC
61
. In response to the control bits and reference current I
REF
the output of DAC
61
is at the potential V
SETP
(and circuit
40
draws current I
DAC-RMR
therefrom). In response to potential V
SETP
, circuit
40
maintains the gate of transistor M
1
at a desired bias potential V
BP
.
More specifically, circuit
40
includes PMOS transistors M
0
and M
1
and capacitor C
P
(connected as shown in FIG.
1
A), transconductance amplifier
50
(whose inverting input is coupled to the output of DAC
61
and whose noninverting input is coupled to the drain of transistor M
0
), resistor R
SETP
(coupled between ground and the inverting input of amplifier
50
), and resistor R
SNSP
(coupled between the drain of M
0
and ground). The gates of transistors M
1
and M
0
are coupled to the output of amplifier
50
, so that the output potential of amplifier
50
is the bias potential V
BP
for the gate of transistor M
1
. Since transistor M
0
has characteristics which match those of transistor M
1
, the current at the drain of M
0
is proportional (with a known proportionality factor) to the current at the drain of M
1
, and the noninverting terminal of amplifier
50
thus receives feedback (from the drain of transistor M
0
) indicative of the drain current of transistor M
1
. In response to this feedback, amplifier
50
maintains the bias potential V
BP
at a level, determined by the reference potential V
SETP
, which will maintain the current through the transducer at a desired nominal level.
Circuit
42
includes NMOS transistor M
2
, capacitor C
N
, and resistors R
CM
, R
DIF1
, and R
DIF2
connected as shown in
FIG. 1A
(with R
CM
connected between ground and Node
1
, R
DIF1
connected between one end of the transducer and Node
1
, and R
DIF2
connected between the other end of the transducer and Node
1
), and transconductance amplifier
52
whose inverting input is coupled to receive bias potential V
CM-SETN
. The noninverting input of amplifier
52
is coupled to Node
1
, and thus is maintained at a potential (above ground) equal to the common mode voltage of the transducer, (V
RMRP
+V
RMRN
)/2, where V
RMRP
−V
RMRN
is the voltage across the transducer (since R
DIF1
=R
DIF2
R
CM
/2, with R
DIF1
typically equal to 20 KOhms). Thus, amplifier
52
(whose output is coupled to the gate of transistor M
2
) forces the gate of M
2
to remain at a bias potential V
BN
, determined by the reference potential V
CM-SETN
, which will maintain the common mode voltage of the transducer at a desired level (typically at or near ground potential).
Still with reference to
FIG. 1A
, the abovediscussed differential output OUT
P
, OUT
N
of the
FIG. 1
circuit (which is indicative of the potential difference across the transducer and is produced at the collectors of transistors Q
P1
and Q
P2
) undergoes amplification in second stage amplifier
51
. The resulting amplified differential output (V
o2N
, V
o2P
) is asserted to a third stage (not shown).
The amplified differential output (V
o2N
, V
o2P
) is also asserted to the inputs of transconductance amplifier
54
. In response, transconductance amplifier
54
asserts a first output having potential V
B3
to the base of transistor Q
P3
and a second output having potential V
B4
to the base of transistor Q
P4
. Current source
56
is coupled between the base of transistor Q
P3
and the top rail, and current source
58
is coupled between the base of transistor Q
P4
and the top rail, as shown. Thus, amplifier
54
determines the difference between bias potentials V
B3
and V
B4
. Circuit
45
(which includes transconductance amplifier
55
) sets the common mode voltage V
B3
+V
B4
)/2 to an appropriate level determined by bias potential V
CM-SET
(which is asserted to the inverting input of transconductance amplifier
55
). The noninverting input of transconductance amplifier
55
is coupled between resistors R
B1
and R
B2
, and resistors R
B1
and R
B2
are connected in series between the base of Q
P3
and the base of QP
4
. The output of amplifier
55
is connected to the common gates of NMOS transistors Q
54
and Q
55
. The drain of Q
55
is coupled to the base of Q
P4
, and capacitor C
B
is coupled between the base of Q
P3
and the base of Q
P4
. Capacitor C
BN
is coupled between the output of amplifier
55
and the bottom rail.
It is well known that any of many different architectures are possible for implementing a preamplifier for a magneto-resistiv
Limbach & Limbach L.L.P.
National Semiconductor Corporation
Patidar Jay
LandOfFree
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