Pre-molded leadframe

Details Pre-molded leadframe Pre-molded leadframe

2002-12-26

2004-09-28

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S670000, C257S676000, C438S123000, C438S124000

Reexamination Certificate

active

06798047

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit chip package technology and, more particularly, to a pre-molded leadframe which is molded in a flat configuration and is adapted for usage in package applications requiring flat substrate technology.
2. Description of the Related Art
Integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as a printed circuit board (PCB). The elements of such a package include a metal leadframe, an integrated circuit die, bonding material to attach the integrated circuit die to the leadframe, bond wires which electrically connect pads on the integrated circuit die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package.
The leadframe is the central supporting structure of such a package. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the leadframe extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the chip package to another component.
For purposes of high-volume, low-cost production of chip packages, a current industry practice is to etch or stamp a thin sheet of metal material to form a panel or strip which defines multiple leadframes. A single strip may be formed to include multiple arrays, with each such array including a multiplicity of leadframes in a particular pattern. In a typical semiconductor package manufacturing process, the integrated circuit dies are mounted and wire bonded to respective ones of the leadframes, with the encapsulant material then being applied to the strips so as to encapsulant the integrated circuit dies, bond wires, and portions of each of the leadframes in the above-described manner.
Upon the hardening of the encapsulant material, the leadframes within the strip are cut apart or singulated for purposes of producing the individual semiconductor packages. Such singulation is typically accomplished via a saw singulation process. In this process, a saw blade is advanced along “saw streets” which extend in prescribed patterns between the leadframes as required to facilitate the separation of the leadframes from each other in the required manner.
In current, conventional leadframe design, the leadframe does not define a continuous, uninterrupted surface. Rather, individual leads of the leadframe are separated from each other and from the peripheral edge of a die pad (if included in the leadframe) by narrow gaps. The die pad of the leadframe, if included therein, is the supporting structure to which the die is typically attached.
It is known in the electronics industry that certain semiconductor package applications (e.g., vision packages) require flat substrate technology. In the specific case of vision packages, the active area of the die electrically connected to the substrate via bond wires cannot be inhibited, and thus cannot be overmolded with a clear plastic encapsulant or compound. In such packages, an optical subassembly is placed over the die and attached to the substrate. The above-described leadframe is typically not suited for use in a vision package application since the optical subassembly requires a generally continuous, planar surface for proper mounting not provided by a conventional leadframe design.
The present invention specifically addresses this deficiency by providing a leadframe that is subjected to a molding process wherein a mold compound is effectively filled within the gaps or spaces between the leads, and between the leads and the die pad (if included). As a result of this molding operation, the filled leadframe defines opposed, generally planar and continuous top and bottom surfaces which allows the same to be used in those package applications requiring flat substrate technology. In the case of vision packages, such filled leadframe can be used as a replacement for two-layer ceramics and/or two-layer PCB substrates typically required for such applications. Thus, the present invention has the advantage of substantially reducing complexity in the manufacturing process, and thus its related costs. These, as well as other features and advantages of the present invention, will be discussed in more detail below.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a semiconductor package comprising a substrate which includes a leadframe having a plurality of leads which each define opposed, generally planar top and bottom surfaces and extend in spaced relation to each other such that gaps are defined therebetween. The substrate further comprises a compound layer which is filled within the gaps defined between the leads, and itself defines opposed, generally planar top and bottom surfaces. The substrate includes a continuous, generally planar top surface collectively defined by the top surfaces of the leads and compound layer, and a continuous, generally planar bottom surface collectively defined by the bottom surfaces of the leads and compound layer. Attached to the top surface is a semiconductor die which is electrically connected to the top surfaces of at least some of the leads via conductive wires.
The substrate of the present invention is adapted for use in those package applications requiring flat substrate technology. One such package is a vision package wherein the substrate can be used as a replacement for two-layer ceramics and/or two-layer PCB substrates typically required for such application.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 2596993 (1952-05-01), Gookin
patent: 3734660 (1973-05-01), Davies et al.
patent: 3838984 (1974-10-01), Crane et al.
patent: 4054238 (1977-10-01), Lloyd et al.
patent: 4189342 (1980-02-01), Kock
patent: 4258381 (1981-03-01), Inaba
patent: 4289922 (1981-09-01), Devlin
patent: 4301464 (1981-11-01), Otsuki et al.
patent: 4332537 (1982-06-01), Slepcevic
patent: 4417266 (1983-11-01), Grabbe
patent: 4451224 (1984-05-01), Harding
patent: 4530152 (1985-07-01), Roche et al.
patent: 4707724 (1987-11-01), Suzuki et al.
patent: 4737839 (1988-04-01), Burt
patent: 4756080 (1988-07-01), Thorp, Jr. et al.
patent: 4812896 (1989-03-01), Rothgery et al.
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4862246 (1989-08-01), Masuda et al.
patent: 4907067 (1990-03-01), Derryberry
patent: 4920074 (1990-04-01), Shimizu et al.
patent: 4935803 (1990-06-01), Kalfus et al.
patent: 4942454 (1990-07-01), Mori et al.
patent: 4987475 (1991-01-01), Schlesinger et al.
patent: 5029386 (1991-07-01), Chao et al.
patent: 5041902 (1991-08-01), McShane
patent: 5059379 (1991-10-01), Tsutsumi et al.
patent: 5065223 (1991-11-01), Matsuki et al.
patent: 5070039 (1991-12-01), Johnson et al.
patent: 5087961 (1992-02-01), Long et al.
patent: 5091341 (1992-02-01), Asada et al.
patent: 5096852 (1992-03-01), Hobson
patent: 5157480 (1992-10-01), McShane et al.
patent: 5172213 (1992-12-01), Zimmerman
patent: 5172214 (1992-12-01), Casto
patent: 5200362 (1993-04-01), Lin et al.
patent: 5200809 (1993-04-01), Kwon
patent: 5214845 (1993-06-01), King et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5218231 (1993-06-01), Kudo
patent: 5221642 (1993-06-01), Burns
patent: 5250841 (1993-10-01), Sloan et al.
patent: 5252853 (1993-10-01), Michii
patent: 5258094 (1993-11-01), Furui et al.
patent: 5266834 (1993-11-01), Nishi et al.
patent: 5273938 (1993-12-01), Lin et al.
patent: 5277972 (1994-01-01), Sakumoto et al.
patent: 5278446 (1994-01-01), Nagaraj et al.
patent: 5279029 (1994-01-01), Burns
patent: 5294897 (1994-03-01), No

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