Pre-emphasis circuit

Details Pre-emphasis circuit Pre-emphasis circuit

2006-07-27

2008-03-18

Nguyen, Khai M. (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

C341S100000

Reexamination Certificate

active

07345602

ABSTRACT:
Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.

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T. Tanahashi et al., “A 2Gb/s 21CH Low-Latency Transceiver Circuit for Inter-Processor Communication,” ISSCC-2001, Session 4 High Speed Digital Interfaces, 2 pp., pp. 60-61, no month.

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