Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-07-26
2002-11-26
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S723000
Reexamination Certificate
active
06486545
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the packaging of electronic components. More particularly, the present invention relates to a ball grid array package.
2. Description of the Related Art
Ball grid array (BGA) packages are well known to those of skill in the art. BGA packages contained an electronic component. The electronic component was mounted to a substrate. The bond pads of the electronic component were electrically connected to a plurality of solder balls, sometimes called interconnection balls, on a lower surface of the substrate of the BGA package. The solder balls were arranged in an array hence the name ball grid array package.
Advantageously, by arranging the solder balls in an array, a high density of interconnects could be formed in a relatively small area. For this reason, the BGA package became increasingly popular as the number of required interconnects to the electronic component increased.
However, as the art moved to smaller and lighter weight electronic devices, it became increasingly important that the thickness of the BGA package used within these electronic devices was small. Disadvantageously, the conventional BGA package was relatively thick. Accordingly, the conventional BGA package was not well suited for use with smaller and lighter weight electronic devices.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a ball grid array (BGA) package includes a substrate having a central aperture. Electrically conductive traces are coupled to a lower surface of the substrate. An electronic component is flip chip mounted to first ends of the traces by electrically conductive bumps, the traces supporting the electronic component in the central aperture.
Electrically conductive interconnection balls are formed on second ends of the traces. The interconnection balls extend from the second ends of the traces, through the substrate, and protruding above a second surface of the substrate.
Advantageously, the BGA package is relatively thin compared to prior art BGA packages. In particular, by mounting the electronic component in the central aperture, the thickness of the BGA package is minimized. Accordingly, the BGA package is well suited for use with miniature lightweight electronic devices, which require thin and lightweight BGA packages.
In accordance with an alternative embodiment of the present invention, a stacked BGA package includes an upper substrate having a first central aperture. Electrically conductive upper traces are coupled to a lower surface of the upper substrate, the upper traces comprising pinholes. A first electronic component is flip chip mounted to first ends of the upper traces by electrically conductive first bumps, the upper traces supporting the first electronic component in the first central aperture.
The stacked BGA package further includes a lower substrate having a second central aperture. Electrically conductive lower traces are coupled to a lower surface of the lower substrate. A second electronic component is flip chip mounted to first ends of the lower traces by electrically conductive second bumps, the lower traces supporting the second electronic component in the second central aperture.
Interconnection rods extend from the lower traces, through the lower substrate, through the pinholes, through the upper substrate, and to a height above an upper surface of the upper substrate.
Advantageously, since the interconnection rods pass through the pinholes, the interconnection rods are locked to the upper traces. Accordingly, the reliability of the electrical connection between the interconnection rods and the upper traces is extremely high. In this manner, the reliability of the stacked BGA package is maximized.
Further, the amount of area on the larger substrate, e.g., printed circuit mother board, allocated for interconnection with the stacked BGA package is reduced compared to mounting the first and second electronic components separately as separate BGA packages. Advantageously, the stacked BGA package in accordance with this embodiment of the present invention is well suited for use with smaller and lighter weight electronic devices.
These and other features and advantages of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.
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US patent application publication US 2001/0054758 by Isaak (Dec. 27, 2001).
Glenn Thomas P.
Hollaway Roy Dale
Webster Steven
Amkor Technology Inc.
Gunnison McKay & Hodgson, L.L.P.
Hodgson Serge J.
Nelms David
Nguyen Thinh T.
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