Pre-decoded instruction cache and method therefor particularly s

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G06F 930

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059702354

ABSTRACT:
An instruction cache for a superscalar processor having a variable byte-length instruction format, such as the X86 format, is organized as a 16K byte 4-way set-associative cache. An instruction store array is organized as 1024 blocks of 16 predecoded instruction bytes. The instruction bytes are prefetched and predecoded to facilitate the subsequent parallel decoding and mapping of up to four instructions into a sequence of one or more internal RISC-like operations (ROPs), and the parallel dispatch of up to 4 ROPs by an instruction decoder. Predecode bits are assigned to each instruction byte and are stored with the corresponding instruction byte in the instruction store array. The predecode bits include bits for identifying the starting, ending, and opcode bytes, and for specifying the number of ROPs that an instruction maps into. An address tag array is dual-ported and contains 1024 entries, each composed of a 20-bit address tag, a single valid bit for the entire block, and 16 individual byte-valid bits, one for each of the 16 corresponding instruction bytes within the instruction store array. A successor array is dual-ported and contains 1024 entries, each composed of a 14-bit successor index, a successor valid bit which indicates that the successor index stored in the successor array should be used to access the instruction store array or that no branch is predicted taken within the instruction block, and a block branch index which indicates the byte location within the current instruction block of the last instruction byte predicted to be executed.

REFERENCES:
patent: 3781808 (1973-12-01), Ahearn et al.
patent: 4044338 (1977-08-01), Wolf
patent: 4155119 (1979-05-01), DeWard et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4179737 (1979-12-01), Kim et al.
patent: 4384343 (1983-05-01), Morganti et al.
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4502111 (1985-02-01), Riffe et al.
patent: 4736288 (1988-04-01), Shintani et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4926322 (1990-05-01), Stimac et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 4992934 (1991-02-01), Portanova et al.
patent: 5056006 (1991-10-01), Acharya et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5131086 (1992-07-01), Circello et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5155816 (1992-10-01), Kohn
patent: 5155820 (1992-10-01), Gibson
patent: 5185868 (1993-02-01), Tran
patent: 5222230 (1993-06-01), Gill et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5233696 (1993-08-01), Suzuki
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5251306 (1993-10-01), Tran
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5367660 (1994-11-01), Gat et al.
patent: 5367703 (1994-11-01), Levitan
patent: 5434985 (1995-07-01), Emma et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5454117 (1995-09-01), Puziol et al.
patent: 5497496 (1996-03-01), Ando
patent: 5606676 (1997-02-01), Grochowski et al.
patent: 5630082 (1997-05-01), Yao et al.
patent: 5758114 (1998-05-01), Johnson et al.
Toyohiko Yoshida et al., "The Approach to Multiple Instruction Execution in the GMICRO/400 Processor," .COPYRGT.1991, pp. 185-195.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, Oct. 24, 1994, pp. 1, 6-11.
Brian Case, "AMD Unveils First Superscalar 29K Core," Microprocessor Report, Oct. 24, 1994, pp. 23-26.
U.S. Patent Application Serial No. 07/929,770 filed Apr. 12, 1992, entitled "Instruction Decoder and Superscalar Processor Utilizing Same", David B. Witte and William M. Johnson.
Mike Johnson, "Superscalar Microprocessor Design", (Prentice Hall series innovative technology), 1991.
H.R. Brandt and P.M. Gannon, "High Speed Buffer with Dual Directories," IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6264-6265.
"System/370 Emulator Assist Processor for a Reduced Instruction Set Computer," IBM Technical Disclosure Bulletin, vol. 30, No. 10, Mar. 1988, pp. 308-309.
Shreekant S. Thakker and William E. Hostmann, "An Instruction Fetch Unit for a Graph Reduction Machine," The 13th Annual International Symposium on Computer Architecture, Jun. 2-5, 1986, pp. 82-91.
Tom R. Halfhill, "AMD K6 Takes on Intel P6," Byte Magazine, Jan. 1996, pp. 67-68, 70 and 72.

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