Pre-charged high-speed comparator

Details Pre-charged high-speed comparator Pre-charged high-speed comparator

2000-10-23

2001-09-18

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000, C327S064000, C365S205000, C365S207000

Reexamination Certificate

active

06292030

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89119112, filed Sep. 18, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a comparator. More particularly, the present invention relates to a comparator capable of receiving different analogue input signals and rapidly producing an output signal that distinguishes between high and low potential.
2. Description of Related Art
For the various types of analogue/digital (A/D) converters (for example, flash ADC, Interpolation ADC, Pipeline ADC and Two-step ADC), high-speed comparator is an essential internal component.
FIG. 1
is the circuit diagram of a conventional comparator. As shown in
FIG. 1
, the devices including PMOS latchp
1
14
, PMOS latchp
2
12
, NMOS latchn
1
20
and NMOS latchn
2
28
together form the regeneration stage of a comparator
28
. The devices including PMOS resetp
1
16
and PMOS resetp
2
10
together form the reset circuit of the comparator
28
. The devices including NMOS minm
22
and NMOS minp
24
together form a group of analogue amplifying circuit in the comparator
28
. The device NMOS strb
26
serves as a current switch for the comparator
28
.
In
FIG. 1
, when a latch signal with a low potential is applied to the input latch terminal of the comparator
28
, the device NMOS strb
26
is in an open-circuit state while the devices NMOS resetp
1
16
and PMOS resetp
2
10
are in a conductive state. Hence, the output terminal outp and the output terminal outn are reset to a voltage vdda. When a latch signal with a high potential is applied to the input latch terminal of the comparator
28
, the device NMOS strb
26
is in a conductive state while the devices NMOS resetp
1
16
and PMOS resetp
2
10
are in an open-circuit state. The group of devices including PMOS latchp
1
14
, PMOS latchp
2
12
, NMOS latchn
1
20
and NMOS latchn
2
18
are triggered to initiate regeneration. The input analogue signal sent to the input terminal inm of the device NMOS minp
24
is compared with the input analogue signal sent to the input terminal inp of the device NMOS minm
22
until the terminal, among the output terminal outp and the output terminal outm, with a higher potential are found.
FIG. 2
is a graph showing the results of simulating the operation of a conventional comparator. As shown in
FIG. 2
, the voltages at the output terminal outp and the output terminal outm must drop from vdda to about ½ vdda before PMOS latchp
1
14
, PMOS latchp
2
12
, NMOS latchn
1
20
and NMOS latchn
2
18
of the regeneration circuit are within the active region and able to find out which of the terminal among the output terminals outp and outm has a higher potential.
Since the voltages at the output terminals outp and outm must drop from vdda (the
3
n
axis position in
FIG. 2
) to about ½ vdda (the
3
.
2
n
axis position in
FIG. 2
) before PMOS latchp
1
14
, PMOS latchp
2
12
, NMOS latchn
1
20
and NMOS latchn
2
18
of the regeneration circuit are within the active region (transistors together have a positive gain), operating speed of the comparator is ultimately limited by the dropping period.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a pre-charged high-speed comparator capable of speeding up the time required for bringing a regeneration circuit into an active region, thereby increasing the overall operating speed of the comparator.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a pre-charged high-speed comparator. The comparator includes a first negative phase logic switch, a second negative phase logic switch, a third negative phase logic switch, a pre-charged high-speed comparator, a first positive phase logic switch, a fourth negative phase logic switch, a second positive phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch and a fifth positive phase logic switch.
A first terminal of the first negative phase logic switch is connected to a power source terminal. The signal terminal of the first negative phase logic switch receives a biased voltage signal. A first terminal of the second negative phase logic switch is connected to a power source terminal. A second terminal of the second negative phase logic switch is connected to a second terminal of the first negative phase logic switch. The signal terminal of the second negative phase logic switch receives a latch signal.
A first terminal of the third negative phase logic switch is connected to the second terminal of the first negative phase logic switch. A second terminal of the third negative phase logic switch is connected to a first output terminal of the pre-charged high-speed comparator. A signal terminal of the third negative phase logic switch is connected to a second output terminal of the pre-charged high-speed comparator. A first terminal of the first positive phase logic switch is connected to the second terminal of the third negative phase logic switch. A signal terminal of the first positive phase logic switch is connected to a signal terminal of the third negative phase logic switch. A first terminal of the fourth negative phase logic switch is connected to the second terminal of the second negative phase logic switch. A second terminal of the fourth negative phase logic switch is connected to the second output terminal of the pre-charged high-speed comparator. A signal terminal of the fourth negative phase logic switch is connected to the first output terminal of the pre-charged high-speed comparator. A first terminal of the second positive phase logic switch is connected to the second terminal of the fourth negative phase logic switch. A signal terminal of the second positive phase logic switch is connected to the signal terminal of the fourth negative phase logic switch.
A first terminal of the third positive phase logic switch is connected to the signal terminal of the third negative phase logic switch. A second terminal of the third positive phase logic switch is connected to the signal terminal of the fourth negative phase logic switch. A signal terminal of the third positive phase logic switch receives a reset signal. A first terminal of the fourth positive phase logic switch is connected to the second terminal of the first positive phase logic switch. A second terminal of the fourth positive phase logic switch is connected to ground. A signal terminal of the fourth positive phase logic switch receives a first analogue signal. A first terminal of the fifth positive phase logic switch is connected to the second terminal of the second positive phase logic switch. A second terminal of the fifth positive phase logic switch is connected to ground. A signal terminal of the fifth positive phase logic switch receives a second analogue signal.
When the latch signal and the reset signal are both high, no current passes into the pre-charged high-speed comparator and the third positive phase logic switch shorts the first output terminal and the second output terminal of the pre-charged high-speed comparator so that the first output terminal and the second output terminal of the pre-charged high-speed comparator approach a ground voltage. A little while before the latch signal changes from a high potential to a low potential, the biased voltage signal changes from a high potential to a low potential. Hence, current flows in from the first negative phase logic switch and the first output terminal and the second output terminal of the pre-charged high-speed comparator is raised to a voltage of about half of the power source voltage. Thus, the third negative phase logic switch, the fourth negative phase logic switch, the first positive phase logic switch and the second positive phase logic switch are lead into a preparatory working state. Subsequently, when the latch signal changes from a high potential to a low potential, the signal resulting from a compa

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