Pre-charge step determining circuit of a generic bit line, parti

Details Pre-charge step determining circuit of a generic bit line, parti Pre-charge step determining circuit of a generic bit line, parti

1997-04-07

2000-05-09

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

365194, 365203, 365210, 3652335, G11C 700

Patent

active

060612738

ABSTRACT:
A pre-charge step determining circuit of a generic bit line, particularly for non-volatile memories, including in one embodiment, circuitry for simulating the selection/deselection of a generic bit line of a memory device; circuitry for simulating the pre-charging of a bit line; and circuitry for determining when the working point of the bit line is reached; the selection/deselection simulation circuitry activating the pre-charging simulation means, which in turn activate the working point attainment determining circuitry, which generate a pre-charge end signal so as to define a minimal duration of the pre-charging that is closely correlated with the characteristics of the actual selection/deselection and pre-charge circuits of the memory device, with the supply conditions, and with the propagation of a generic bit line, the pre-charge simulation circuitry and the working point attainment determining circuitry being activated synchronously with respect to a new reading cycle of the memory device.

REFERENCES:
patent: 5029135 (1991-07-01), Okubo
patent: 5083047 (1992-01-01), Horie et al.
patent: 5210715 (1993-05-01), Houston
patent: 5404334 (1995-04-01), Pascucci et al.
patent: 5457661 (1995-10-01), Tomita et al.
Patent Abstracts of Japan, vol. 18, No. 89 (P-1692), Feb. 14, 1994 & JP-A-05 290592 (Matsushita Electronics Ind. Co.).
IBM Technical Disclosure Bulletin, vol. 33, No. 4, Sep. 1990, New York, US, pp. 257-258, "Sense Amplifier Set Control".

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