Pre burn-in thermal bump card attach simulation to enhance relia

Details Pre burn-in thermal bump card attach simulation to enhance relia Pre burn-in thermal bump card attach simulation to enhance relia

1998-08-05

2000-09-05

Picardat, Kevin M.

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438 14, 438 17, G01R 3126, H01L 2166

Patent

active

06114181&

ABSTRACT:
The present invention provides a method for detecting integrated circuit component failures that would normally be triggered during the final card attach step of the manufacturing process. According to the preferred embodiments of the present invention, integrated circuit modules are subjected to an environment that simulates a card attach process step. The process step that simulates the card attach process is introduced into the fabrication process prior to the standard integrated circuit reliability testing procedures, thereby inducing or accelerating failure of certain weak modules and allowing for identification of faulty modules during the subsequent reliability testing steps.

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