Patent
1997-09-30
1999-02-16
Shah, Alpesh M.
395376, 395280, G06F 1576
Patent
active
058729860
ABSTRACT:
A pre-arbitrated bypassing system in a speculative execution microprocessor is provided. The bypassing system provides execution units enhanced to include a comparator and an enabled driver. The comparator compares a bypass address that is broadcast upon instruction decode with the destination address within each execution unit. If there is a match, then the result data is driven onto the bypass bus. Additionally, a suppress signal and validation scheme/apparatus are included to ensure that valid data is being driven onto the bypass bus. A bypass bus and associated apparatus may be included for every potential source operand.
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Intel Corporation
Shah Alpesh M.
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