Powerup control of PLL

Details Powerup control of PLL Powerup control of PLL

2005-10-18

2005-10-18

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C331S010000, C331S17700V

Reexamination Certificate

active

06956416

ABSTRACT:
An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.

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patent: 6597249 (2003-07-01), Chien et al.
patent: 6806781 (2004-10-01), Bisanti et al.

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