Powergating method and apparatus

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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C327S055000

Reexamination Certificate

active

10900505

ABSTRACT:
A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.

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Min, Kyeong-Sik, Kawaguchi, Hiroshi, Sakurai, Takayasu, Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era, ISSCC 2003/Session 22/TD: Embedded Technologies/ Paper 22.8, 2003 IEEE International Solid-State Circuits Conference, Feb. 12, 2003/ Salon 1-6, pp. 10.

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