Power-up reset override architecture and circuit for flash memor

Details Power-up reset override architecture and circuit for flash memor Power-up reset override architecture and circuit for flash memor

1993-06-30

1994-09-06

Popek, Joseph A.

Static information storage and retrieval

Powering

Conservation of power

365185, 365218, 365900, G11C 800

Patent

active

053454243

ABSTRACT:
A reset circuit in a system comprising a microprocessor coupled to a flash memory by a system bus. The reset circuit has a reset signal generation circuit, a sleep signal generation circuit and a reset override signal generation circuit. The reset signal generation circuit generates a reset signal when power is applied to the flash memory. The reset signal causes the flash memory to enter a predetermined reset state. The sleep signal generation circuit is coupled to the reset signal generation circuit. The sleep signal generation circuit generates a sleep signal. The sleep signal causes the reset signal generation circuit to enter an energy saving sleep mode when the flash memory is placed in the sleep mode. The reset signal causes the sleep signal generation circuit to reset and suppress generation of the sleep signal. The reset override signal generation circuit is coupled to the reset signal generation circuit. The reset override signal is generated during power-up. The reset override signal forces the reset signal generation circuit to generate the reset signal during power-up even if the reset signal generation circuit is receiving the sleep signal. The reset signal override circuit draws substantially no power when the flash memory is placed in the sleep mode.

REFERENCES:
patent: 5243575 (1993-09-01), Sambandan et al.
patent: 5247655 (1993-09-01), Khan et al.
patent: 5262998 (1993-11-01), Mnich et al.

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