Power up reset circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307594, 307475, 3072964, H03K 1730

Patent

active

051592061

ABSTRACT:
A circuit to generate a power up reset pulse for a semiconductor device, such as a dynamic random access memory (DRAM) that may utilize an on chip voltage generator is disclosed. The circuit generates a positive going pulse when the external power supply ramps up. The pulse disappears when the voltage level within the device reaches a predetermined value of the external supply voltage. The circuit includes a CMOS inverter that is biased between the external voltage and ground and has its input coupled to the internally regulated voltage. The gate of a pull down transistor may couple the input of the CMOS inverter to the internally regulated voltage. A pull up transistor that is biased by the external voltage and whose gate is connected to the output of the CMOS inverter, is connected to the input of the CMOS inverter. Other elements may be added to enhance the circuits performance. The trip point of the circuit with respect to the externally supplied voltage may be adjusted by varying the relative sizes of the pull down transistor and the pull up transistor.

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