Power-up/power-down detection circuit

Details Power-up/power-down detection circuit Power-up/power-down detection circuit

1999-02-08

2003-07-15

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S143000, C327S543000

Reexamination Certificate

active

06593790

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of power-up voltage detectors, and in particular to a power-up voltage detector which has improved linearity, sensitivity, and temperature characteristics.
BACKGROUND TO THE INVENTION
A power-up detector is used to detect the existence of a power supply voltage level which enables other circuits to operate correctly. A power-up detector typically generates a pulse that starts when the supply voltage is sufficient to supply the pulse, and ends when the supply voltage is sufficient to enable other circuits to operate correctly. The pulse is used to initialize the other circuits, and is thus typically required to be guaranteed to have a predetermined minimum duration. The circuits require the reset pulse as soon as possible during the power-up period firstly to minimize the time between the application of power and the functionality of the circuits, and secondly to avoid dangerous conditions in non-reset circuits during the power-up period.
One prior art approach for a power-up reset circuit described in U.S. Pat. No. 5,111,067 issued to Wong et al, uses two current mirrors and transistor threshold voltages to determine the reset trigger point. The current mirrors allow for very early power supply voltage detection, but using transistor threshold voltages which vary with process and temperature variations as well as with repetitive power-up/power-down cycles, will cause the reset pulse to be generated either too soon, too late or not at all, and thus the overall sensitivity of the power-up reset circuit is greatly decreased.
To address this shortfall, another prior art approach described in U.S. Pat. No. 5,654,656 issued to Geannopoulos, uses a number of transistors which are added as switches designed to reduce the biases which can lead to shifted threshold voltages caused by repetitive power-up/power-down transitions. The essential operation is still the same as in the preceding prior art embodiment of Wong et al, however, and still requires the PMOS feedback transistor as a threshold detector. Typically, PMOS transistors have a higher threshold voltage V
TP
than NMOS transistor threshold voltages, and the saturation current in a PMOS transistor is three times as large as the saturation current in an NMOS transistor of the same size. Furthermore, the circuit has a non-linear operating current-voltage characteristic which makes it highly susceptible to temperature and process variations.
Another concern in addition to power-up detection is power supply voltage bump detection. This type of circuit detects when the power supply falls below an acceptable operating range. A reset pulse to circuitry utilizing the power supply must be provided to only enable the circuits once the power supply has once again reached the operating range. A circuit which could also be used as a power-up detector, in addition to the voltage bump detection for which it is designed, is described in U.S. Pat. No. 5,686,848 issued to Mes et al. The circuit provides a reset pulse during a short interval when the power supply voltage is below a nominal operating range. The circuit described therein uses the power supply voltage and a reduced version thereof, to control the operation of a PMOS and an NOMS transistor respectively, connected in series between a charge storing node and ground. As the power supply voltage level decreases due to the action of a voltage bump, the PMOS transistor conducts more than the NMOS and enables current conduction in a reset pulse generating circuit. As the power supply voltage level subsequently increases due once again to the action of the voltage bump, the NMOS transistor conducts more than the PMOS transistor and as a result, the current conduction in the reset pulse generating circuit is ceased. The result is the generation of a reset pulse, the trailing edge of which can be used to reset a circuit that depends on the power supply voltage being above a particular value. This power-up/power-down reset circuit can also be used for power-up detection but cannot detect the power-up condition until the power supply has reached approximately 3V
TN
. However, waiting to issue the power-up reset pulse until this level is reached can be dangerous to internal circuits, as previously described.
A need therefore arises for a simple and versatile power-up detection circuit which has improved linear performance and has compensation for temperature and process variations.
SUMMARY OF THE INVENTION
The present invention provides a power-on detection circuit which is highly linear, can detect very low voltage, such as 500 mV, and compensates for temperature and process variations.
In accordance with an embodiment of the invention, a current mirror is used, which provides very low voltage detection. In addition one of the FETs of the current mirror constitutes one of the FETs of a CMOS inverter which provides a current conduction path for a reset circuit.
In accordance with another embodiment, a power-up detector for detecting power-up and power supply voltage bump conditions is comprised of a current mirror connected to a power supply, a pair of series connected resistors connected between the current mirror and ground, and providing a bias point at a junction of the series connected resistors, and a field effect transistor having a source-drain circuit connected between the current mirror and ground for providing an output signal, the transistor being controlled by the bias point.
In accordance with another embodiment, a power-up detector is comprised of a first PMOS FET having its source connected to a positive power supply, a pair of resistors connected in series between the drain of the FET and ground, a second PMOS FET having its source-drain circuit connected in series with an NMOS FET between the positive voltage power supply and ground, the gates of the first and second PMOS FETs being connected together, the gate of the NMOS FET being connected to a junction between the resistors, and an output node at the junction of the second PMOS FET and the NMOS FET.
In accordance with another embodiment, a power-up detector is comprised of an FET current mirror comprised of a pair of similar polarity FETS connected to a voltage rail, and being further comprised of a pair of series connected resistors connected to ground, one of the FETs forming one FET of a CMOS inverter, a gate of another of the FETs of the CMOS inverter being connected to a junction between the resistors, the junction between the first and another FETs of the CMOS inverter providing an output signal.
In accordance with another embodiment, a power-up detector comprises a first PMOS FET having its source connected to a positive voltage rail, a pair of resistors connected in series between its drain and ground, a CMOS inverter comprising a second PMOS FET having its source-drain circuit connected in series with an NMOS FET between the positive voltage rail and ground, the gates of the PMOS FETs being connected together, the gate of the NMOS FET being connected to a junction between the resistors, an output node at the junction of the second PMOS FET and the NMOS FET, and means for fixing the voltage at the junction of the gates of the PMOS FETs.
In accordance with another embodiment, a power-up detector comprises a first NMOS FET having its source connected to a ground voltage rail, a pair of resistors connected in series between its drain and a positive voltage rail, an CMOS inverter comprising a second NMOS FET having its source-drain circuit connected in series with a PMOS FET between the ground voltage rail and the positive voltage rail, the gates of the NMOS FETs being connected together, the gate of the PMOS FET being connected to a junction between the resistors, an output node at the junction of the second NMOS FET and the PMOS FET, and means for fixing the voltage at the junction of the gates of the NMOS FETs.


REFERENCES:
patent: 3925718 (1975-12-01), Wittlinger
patent: 5442312 (1995-08-01), Walter
patent: 5838188 (1998-11-01), Taguchi

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