Power-up input bias circuit and method

Details Power-up input bias circuit and method Power-up input bias circuit and method

1997-12-29

1999-08-10

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327143, 327546, H03K 1722

Patent

active

059364475

ABSTRACT:
A circuit and method biases signal pins, such as the output enable pin and other input pins, of an integrated circuit to a predetermined level during power-up of the integrated circuit. The circuit can be incorporated into the chip-level design of the integrated circuit, such as a CMOS device. The circuit has a pull-up/pull-down biasing section, a sensing section, and a latch section to bias the output enable signal to a disabled or inactive level during power-up. A bus hold section can additionally be provided to bias the other input pins of the integrated circuit to a fixed, solid logic level during power up. When an external output enable input is applied to activate the output enable pin, the circuit releases the bias applied to the output enable pins and the other input pins.

REFERENCES:
patent: 5638330 (1997-06-01), Confalonieri et al.
patent: 5703475 (1997-12-01), Lee et al.
patent: 5734280 (1998-03-01), Sato

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