Static information storage and retrieval – Powering
Reexamination Certificate
2000-02-23
2002-03-26
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Powering
C365S195000, C327S143000
Reexamination Certificate
active
06363025
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuits for performing electrical functions beginning from an initial condition after the application of a power signal and an input signal.
BACKGROUND OF THE INVENTION
As one example of an integrated circuit (IC) that begins operation from an initial condition after the application of a power signal, consider a dynamic random access memory (DRAM) formed on a substrate. Such an IC conventionally accepts an externally applied power signal (V
CCX
) on one of its contacts. To operate, V
CCX
is applied with a voltage in a range including 5 volts measured relative to a ground contact. For retaining data stored in the memory while it operates, V
CCX
is supplied from a battery in a range including 3.3 volts. Operation from an initial condition follows, for example, two different types of transitions: the transition from 0 volts to 5 volts for beginning operation of the DRAM, and the transition from 3.3 volts to 5 volts for resuming operation of a DRAM containing previously stored data.
Whether beginning with or without previously stored data, circuits within the DRAM may not correspond to the initial condition until after receiving an initialization signal. Conventional initialization signals include a pulse having a leading edge generated when a change in the applied power signal is detected, and a trailing edge generated when a predetermined time period has lapsed. The conventional timer circuit used for generation of the initialization signal does not operate properly when the voltage of the applied power signal changes too slowly.
Improper operation is most apparent when the timer circuit used to generate the initialization pulse includes a current source driven from V
CCX
. The current source provides a regulated current for charging a capacitor of substantial capacitance. When the voltage developed on the capacitor exceeds a threshold, the trailing edge of the initialization pulse is generated. But, when the voltage of V
CCX
rises slowly over a considerable time, for example 6 milliseconds per volt, the voltage on the capacitor may exceed the threshold before V
CCX
is of sufficient magnitude to achieve reliable initialization.
Proper operation depends on reliable initialization, even when the applied V
CCX
signal cannot be generated with a sufficiently rapid transition to the operating level. When an integrated circuit such as a DRAM is not properly initialized, i.e. does not begin from a predetermined initial condition, inaccurate data may be recalled or new data may not be accurately stored. System failure is likely to result from use of such unreliably stored data.
Memory devices are commonly used in a wide variety of system designs, including computer, telecommunications, banking, video, and audio equipment, to name a few major applications. When system performance requires additional memory capability, such as proper operation in spite of slowly varying power supply voltage, it is desirable to deliver such additional capability without adversely affecting other aspects of the system design. In other words, it is desirable for improved memory to be compatible with existing system designs so that expensive redesign can be avoided.
In view of the problems described above and related problems that consequently become apparent to those skilled in the applicable arts, the need remains in integrated circuit technology for a power up initialization circuit that, among other capabilities, operates reliably when the applied power signal is characterized by a slow transition to an operating power level.
SUMMARY OF THE INVENTION
Accordingly, an integrated circuit (IC) in one embodiment of the present invention performs an electrical function beginning from an initial condition. The IC is responsive to a power signal and an input signal. The input signal is received after the power signal is received. The IC includes a signal generator and a subcircuit, each powered by the power signal.
The signal generator generates a first signal in response to the power signal and a second signal in response to the input signal. The subcircuit is coupled to the signal generator and performs the electrical function so that performance, in response to the second signal, is from the initial condition.
According to a first aspect of such an embodiment, performance of the electrical function is stayed after receipt of the first signal and performance begins from the initial condition after the second signal has been received. By generating the second signal in response to the input signal, proper initialization can be achieved because the signal generator is not responsive to the rate of change of transitions of the power signal.
According to another aspect, the first and second signals are generated by a flip flop so that the time between generation of the first signal and the generation of the second signal is less dependent on changes of the power signal voltage. That is to say that the power signal voltage is not used to measure time.
According to yet another aspect, the flip flop attains a state for generating the first signal by the application of the power signal voltage, without more. By generating the first signal as soon as the power signal is applied, more time is available for the process of staying performance of the IC's electrical functions and of resetting so that performance may begin immediately after receipt of the second signal.
In an alternate embodiment, a dynamic memory, of the present invention provides a data signal. The memory is powered by a power signal and is responsive to an address signal, an address strobe, and a first signal. The memory includes a conductor, i.e. a node, for conveying the address strobe and the first signal. In addition, the memory includes a timing circuit, an array of memory cells, and means for addressing.
The timing circuit is powered by the power signal and generates a second signal in response to the power signal. The timing circuit is coupled to the conductor and generates a third signal in response to the input signal.
The means for addressing is also powered by the power signal. This addressing means is operable from an initial condition in response to the third signal. The addressing means identifies a selected memory cell of the array in response to the address signal and the address strobe. The addressing means also provides the data signal responsive to data stored in the selected memory cell.
According to a first aspect of such a memory, the first signal and the address strobe are conveyed on the same conductor so that systems designed to provide several occurrences of the address strobe signal to a conventional memory are compatible with memory of the present invention. The first occurrence of an address strobe provided to a memory of the present invention, therefore, operates as the first signal.
According to another aspect of such a memory, the time between application of the power signal and receiving the first signal is conventionally accommodated by system design rules. By providing the second signal in response to the power signal and the third signal in response to the first signal, the time available for memory initialization depends on system design rules rather than on the transition time for attaining power supply voltage. As systems are expanded, transition times typically degrade by additional system power supply distribution and loading factors. Memory of the present invention when installed in a system subject to such expansion is less likely to be adversely affected by system expansion.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations partic
Schwegman Lundberg Woessner & Kluth P.A.
Zarabian A.
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