Power up/down sequence scheme for memory devices

Details Power up/down sequence scheme for memory devices Power up/down sequence scheme for memory devices

2008-05-12

2010-02-16

Mai, Son L (Department: 2827)

Static information storage and retrieval

Powering

C365S227000

Reexamination Certificate

active

07663959

ABSTRACT:
A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected.

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