Power up detect circuit for configurable logic array

Details Power up detect circuit for configurable logic array Power up detect circuit for configurable logic array

1993-02-09

1994-06-07

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307290, 307465, H03K 1722

Patent

active

053192559

ABSTRACT:
The present invention provides power up detect circuit for generating a reset signal for a logic circuit that includes N-channel transistors having a threshold value Vnth and P-channel transistors having a threshold value Vpth. The power-up detect circuit includes comparison means having first and second inputs; clamping means for clamping the first comparison means input at X*Vnth above ground potential; and monitoring means connected to the second comparison means input and responsive to ramp up of a power supply voltage for holding the second comparison means input at X*Vpth less than the power supply voltage whereby the comparison means output switches from an inactive state to an active state when the power supply to ground potential reaches (X*Vnth)+(X*Vpth). The power up detect circuit further includes hysteresis means connected between the comparison means output and the second comparison means input and responsive to the power supply for preventing the comparison means output from switching from the active state to the machine state if the power supply voltage remains above (X*Vnth+Y*Vpth)-(WVnth+ZVpth), where 0<W<X, 0<Z<Y).

REFERENCES:
patent: 3753011 (1973-08-01), Faggin
patent: 3983420 (1976-09-01), Kikuchi
patent: 4649292 (1987-03-01), Rusznyak
patent: 4874965 (1989-10-01), Campardo et al.
patent: 5187389 (1993-02-01), Hall et al.

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