Power-up control circuit with a power-saving mode of operation

Details Power-up control circuit with a power-saving mode of operation Power-up control circuit with a power-saving mode of operation

2002-10-01

2004-05-11

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C365S228000, C365S229000, C365S233100, C327S143000

Reexamination Certificate

active

06735142

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention.
This invention relates to a power-up control circuit for a semiconductor memory device and, more particularly, to a power-up control circuit that accommodates a power saving mode of operation, such as a deep-sleep mode of operation.
2. Prior Art.
When a semiconductor memory device is in a deep sleep mode of operation, all internal voltage regulators and any internal reference voltage generators are turned off to save power. In the deep-sleep mode, only a voltage from an external power supply is supplied to the memory device so that the semiconductor memory device is no longer operational in the deep-sleep mode of operation. After the deep-sleep mode of operation is completed, all data in the memory device is reset and the memory device goes through a normal power-up sequence. In a normal power-up sequence, all of the circuitry has to be initialized and all internal voltage regulators must be set up to operate in the normal mode of operation, followed by a power-up sequence and a memory data reset.
Previously known power-up control circuits cannot provide recovery from a deep-sleep mode of operation because they work by detecting a change in the level of the external voltage supply, which does not change in a power-saving mode such as a deep sleep mode of operation.
Consequently, a need exists for a power-up control circuit for a semiconductor memory device that accommodates a power-saving mode of operation, such as a deep-sleep mode of operation.
SUMMARY OF THE INVENTION
After a semiconductor memory device is initially turned on and after a power-up detection circuit determines that an external voltage has reached a predetermined level, a normal power-up NPWRUP signal goes to an active HIGH state to start a power-up sequence for the device. When the device is in a special mode of operation, such as a deep-sleep mode that is used to save power in, for example, low-power devices such as dynamic random access memory DRAM cells. In the deep-sleep mode of operation all memory cell data and all register data disappear because the internal reference sources and all internally regulated voltage are disabled. To accommodate a power-saving mode of operation such as a deep-sleep mode of operation, the present invention provides a power-up control circuit that has three component circuits including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply voltage level detection section and the special command detecting section to provide a combined power-up control signal CPWRUP.
In the present invention, a power-up detection circuit and a power-up sequence for initialization of the memory device are the same as those for a normal power-up control circuit for an initial power-up operation. However, in the present invention, the combined power-up control signal CPWRUP is able to be temporarily brought to a LOW state for a predetermined period of time immediately after the end of a deep-sleep mode of operation. The LOW state of the combined power-up control signal CPWRUP allows all internal circuitry to be reset to their initial states that are the same as those obtained after a normal power-up sequence, even though the external voltage level stays at its normal level.
One preferred embodiment of the invention provides a memory-circuit power-up control circuit with a power-saving mode of operation with a normal power-up voltage level detection circuit; a special-command detection circuit; and a combined output driver circuit. The normal power-up voltage level detection circuit senses the level of an external supply voltage VDD and provides a normal power-up level detection output signal NPWRUP when the level of the VDD supply voltage exceeds a predetermined voltage level. The special-command detection circuit receives a power-saving enable input control signal ZZE and provides a special-command detection control output signal. The special-command detection circuit has an initialization pulse generator that provides an initialization control pulse signal that has a predetermined duration and that is triggered by the trailing edge of an active ZZE signal. The special-command detection control output signal is active either when the power-saving enable input control signal ZZE is active or when the initialization control pulse signal is inactive. The combined output driver circuit receives the normal power-up level detection output signal NPWRUP and the special command output signal and provides at an output terminal a combined power-up output signal CPWRUP that is normally active when the normal power-up level detection output signal NPWRUP is active and when either the ZZE signal is active or the ZZE delay signal is inactive.
The combined output driver circuit includes a logical AND function that combines the output signal NPWRUP of the normal power-up level detection circuit and special-command detection control output signal. The logical AND function is provided by a NAND gate and an inverter that drives the output terminal of the combined output driver circuit. The special command detection circuit includes a logical OR function that combines the ZZE input signal and an inverted initialization control pulse to provide the special-command detection control output signal.
The present invention provides a method of controlling a power-up function of a memory circuit to accommodate a power-saving mode of operation. The method includes the steps of: sensing the level of a an external voltage VEXT and providing an active normal power-up NPWRUP signal when the level of the external voltage exceeds a predetermined level; receiving a deep-sleep command signal ZZE in a special command detection section; providing an active special power-up output signall during the active time of the ZZE signal; triggering a pulse generator on the trailing edge of the ZZE signal to provide an initialization control pulse having a predetermined duration; providing an active special-command detection control output signal either when the power-saving enable Input control signal ZZE is active or when the initialization control pulse signal is inactive; and logically combining the normal PWRUP output signal with the special-command detection control output signal to provide a combined power-up output signal that is active during an active normal PWRUP signal except for the time of the inactive special PWRUP signal having the predetermined duration.


REFERENCES:
patent: 5495453 (1996-02-01), Wojciechowski et al.
patent: 5610542 (1997-03-01), Kang et al.
patent: 5767710 (1998-06-01), Cho
patent: 5942925 (1999-08-01), Stahl
patent: 6104221 (2000-08-01), Hoon

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