Power-up circuit with hysteresis for an output buffer

Details Power-up circuit with hysteresis for an output buffer Power-up circuit with hysteresis for an output buffer

1989-12-20

1991-09-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307360, 307592, 3072964, 307475, H03K 5153, H03K 3284

Patent

active

050516116

ABSTRACT:
An improved power-up circuit for exerting control over output buffer devices in such a way as to disable these buffer devices during the period when the extended circuit is vulnerable to transient effects as the common power supply voltage V.sub.cc is rising during the "power-up" or "power-down" of the extended circuit. One particular such transient effect is the loading down of the power supply due to the buffer devices being in the current-sourcing and in the current-sinking states simultaneously. One improvement over the earlier circuitry is the provision of an asymmetry in the values of V.sub.cc at which control is transferred between the power-up circuit and the rest of the circuit as V.sub.cc is rising during power-up and as V.sub.cc is falling during power-down, respectively. In particular, the design of the present circuit allows control to be exerted over the buffer devices up to a relatively high value of V.sub.cc during power-up without exposing the extended circuit to the risk of being inadvertantly disabled upon the occurrence of noise-induced dip in V.sub.cc after the power supply voltage is up to its operating range. The asymmetry or hysteresis allows the cut-in voltage of the present circuit (during power-down) to be set at a lower value than the cut-out voltage (during power-up). The hysteresis is established by use of a second transistor in the power-up circuit which switches off at the same time that the threshold transistor switches on. A second improvement offered by the present circuit is the speed with which the cutting in and cutting out occurs. This speed is effected by the positive feedback means by which the second transistor is coupled with the switching transistor. As a consequence, the speed of switching is made independent of the edge rate of V.sub.cc.

REFERENCES:
patent: 4254347 (1981-03-01), Ray
patent: 4311927 (1982-01-01), Ferris
patent: 4409501 (1983-10-01), Eickerman et al.
patent: 4481430 (1984-11-01), Houk et al.
patent: 4581550 (1986-04-01), Ferris et al.
patent: 4661727 (1987-04-01), Ferris et al.
patent: 4697103 (1987-09-01), Ferris et al.
patent: 4717840 (1988-01-01), Ouyang et al.
patent: 4948995 (1990-08-01), Takahashi

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