Power transition write protection for PROM

Details Power transition write protection for PROM Power transition write protection for PROM

1984-12-10

1986-09-16

Moffitt, James W.

Static information storage and retrieval

Powering

365228, 371 66, G11C 2900, G11C 700

Patent

active

046126325

ABSTRACT:
A power transition detection and override circuit is coupled to the OUTPUT-ENABLE (OE) pin of a nonvolatile electrically erasable programmable read only memory (EEPROM) for preventing inadvertent write commands thereto from a microprocessor arising from supply voltage (V.sub.cc) transitions, including power up and power down. With the EEPROM provided with internal write protection for V.sub.cc less than approximately 3.0 VDC, the power transition detection and override circuit holds the OE pin of the EEPROM low until V.sub.cc reaches a specified operating voltage, e.g., 4.75 VDC. This masks any WRITE ENABLE (WE) line glitches by the read operation of the active low OE line.

REFERENCES:
patent: 4375663 (1983-03-01), Arcara et al.
patent: 4399524 (1983-08-01), Muguruma et al.
patent: 4433390 (1984-02-01), Carp et al.
patent: 4534018 (1985-08-01), Eckert et al.

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