Power transistor protection from substrate injection

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307270, 357 48, H01L 2706, H02M 118, H03K 1766

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active

044968493

ABSTRACT:
A PN junction-isolated bipolar integrated circuit having a power transistor protected from delay in turn-off by a parasitic substrate injection. Protection is obtained by interposing an additional isolation pocket between an isolating pocket producing the substrate injection and an isolation pocket for an input transistor for the power transistor, and coupling the additional isolation pocket to the base of the power transistor.

REFERENCES:
patent: 3676714 (1972-07-01), Wensink
patent: 3931634 (1976-01-01), Knight
patent: 3995307 (1976-11-01), Alcorn et al.
patent: 4079271 (1978-03-01), Peil
patent: 4146801 (1979-03-01), Vali et al.
patent: 4287436 (1981-09-01), Tezuka et al.
patent: 4340922 (1982-07-01), Delaporte
Frederiksen et al., IEEE J. of Solid State Circuits, vol. SC 9, No. 6, Dec. 1974, pp. 394-403.

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