Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
1999-09-23
2001-10-16
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S163000, C257S164000, C257S560000, C257S561000, C257S562000, C257S563000, C257S564000, C257S573000, C257S578000, C257S579000, C257S580000, C257S582000
Reexamination Certificate
active
06303973
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a power transistor and a semiconductor integrated circuit device using the same, and in particular, to such a transistor for use in the drivers of motors and actuators or in speaker drivers for audio systems that require electric current capacity.
2. Description of the Related Art
The structure of conventional power transistors is explained with references to
FIGS. 7 and 8
. The power transistor shown in
FIGS. 7 and 8
is a vertically structured NPN-type power transistor formed within an epitaxial layer
72
of a P-type silicon semiconductor substrate. Vertical-type power transistors are the type in which the carriers that pass through the PN junction mainly diffuse in the vertical direction (the direction of the depth) of the transistor.
FIG. 7
is a plan view showing the surface layout of a power transistor with one emitter region when viewed from above.
FIG. 8
is a plan view showing the surface layout of a power transistor whose emitter region is divided into two by the base region when viewed from above. a low N-type impurity concentration. A base region
75
having P-type impurities is surrounded by the N
−
-type collector region
72
a
, and an emitter region
76
having N-type impurities is formed inside the base region
75
. A base contact
74
is formed on the surface of the base region
75
. The structure of the base contact is shown in
FIG. 9
, where the base contact
91
connects the metal wiring (not shown) with the base region
93
by forming a hole on an insulating layer
92
that covers the surface of the base region, allowing wiring material, such as aluminum, to flow into the hole.
In
FIG. 8
, the power transistor has an N
+
-type collector region
83
having a high N-type impurity concentration arranged in a ring form surrounding an N
+
-type collector region
82
a
with a low N-type impurity concentration. A base region
85
having P-type impurities is surrounded by the N
+
-type collector region
82
a
. Emitter regions
86
a
and
86
b
with N-type impurities are formed inside the base region
85
. A base contact
84
is formed on the surface of the base region located between the emitter regions
86
a
and
86
b.
However, when a power transistor such as the one shown in
FIG. 7
is used, a large current flows in the portion of the base region
75
near where the base contact
74
is formed, because the base contact
74
is in contact with the metal wiring layer. This is because the carriers in the circumference portion of the emitter region
76
near the base contact
74
are in an easy flow state (“easily activated state”) compared with carriers in the center portion of the emitter region
76
far from the base contact
74
. Also, when considering the flow of carriers in the vertical and lateral directions (the horizontal direction along the surface), the circumference portion of the emitter region
76
is closer to the N
+
-type collector region
73
compared with the center portion of the emitter region
76
. Because of this, the carriers in the circumference portion is more easily dissipated to the collector region
73
than the carriers in the center portion.
Therefore, the current density that flows from the emitter region
76
is non-uniform in some of the regions, causing heat to accumulate due to concentration of current, possibly causing safe operating area (SOA) destruction. In order to reduce current concentration in the emitter region
76
to prevent SOA destruction, the width b of the emitter region
76
is narrowed in some devices. But this will reduce the area of the emitter region
76
and result in a decrease in overall current capacity.
When a power transistor as shown in
FIG. 8
is used, in which the overall emitter region area is enlarged by dividing the emitter region into two sections
86
a
and
86
b
, two regions A and B within the emitter region
86
a
and
86
b
(encircled by the broken lines in
FIG. 8
) are created, which areas are closest to both the base contact
84
and the collector region
83
. As current flows from the metal wiring layer to the base region
85
via the base contact
84
, carriers in the regions within the emitter regions
86
a
and
86
b
that are close to the base contact
84
are most easily activated. Because of this, large carrier flow will occur in the portions of the emitter regions close to this type of base contact.
In the aforementioned emitter regions A and B, these regions are in a state where the regions are activated to cause large carrier flow. When the emitter regions of the regions A and B are in such a state, the carrier flow is facilitated because the collector region is also in its proximity. Because of this, the current becomes concentrated in the emitter region in the A and B areas, making the area vulnerable to SOA destruction due to heat caused by the concentration of currents.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a power transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a power transistor and semiconductor integrated circuit devices using the same with improved endurance properties against SOA destruction, by restraining the concentration of currents in the emitter region.
Another objective of the present invention is to obtain improved current capacity for a power transistor and semiconductor IC devices using the same by expanding the area of the emitter region as well as leveling the degree of activation of the carriers in the emitter region which depends on the distance from the base contact and the collector region.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a power transistor comprising in its vertical structure a collector region formed in a semiconductor substrate, a base region formed within the collector region, an emitter region formed within the base region, the emitter region dividing the base region into a first base section and at least one second base section surrounded by the emitter region on the substrate surface, the first and second base sections being connected within the substrate, and a base contact formed on the surface of each second base section. In such a power transistor, localized concentration of current is prevented by forming the base contact away from the collector region and within the section of the base region surrounded by the hoop-shaped emitter region.
According to another embodiment of the present invention, a plurality of base-emitter sections, each formed by a base region divided into two sections on the substrate surface by a hoop-shaped emitter region as described above, are formed within the collector region. By creating a plurality of such base-emitter sections in the power transistor, current concentration is further prevented.
According to yet another embodiment of the present invention, a contiguous emitter region is shaped to divide the base region into a plurality of sections each surrounded by the emitter region on the substrate surface, each surrounded section of the base region having a base contact formed there on. In such a power transistor, the current flow to the base region is stabilized by creating more than one contiguous hoop-shaped emitter region, and by forming a ballasting resistor on the surface of each section of the base region surrounded by the emitter region. The plurality of surrounded base sections may be arranged in a row, or in other geometrical shapes, such as five surrounded sections occupying the four corners and the center of a square. The latter arrangement further reduces current concentration because the surrounded base sections are arranged symmetrically.
In another aspect, the present invention provides a semiconductor integrated circuit device, such as an LSI, comprising a plurality of power transistors with
Nakagawa Eiji
Yamamoto Seiichi
Hogan & Hartson L.L.P.
Lee Eddie
Rohm & Co., Ltd.
Warren Matthew E.
LandOfFree
Power transistor having large electric current capacity and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power transistor having large electric current capacity and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power transistor having large electric current capacity and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2590542