Power transistor

Details Power transistor Power transistor

2001-03-27

2003-04-08

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

C257S570000

Reexamination Certificate

active

06545341

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 U.S.C. 119 to Japanese Patent Application No. P2000-87550 filed Mar. 27, 2000, and Japanese Patent Application No. P2000-251854 filed Aug. 23, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device, more particularly to a bipolar type semiconductor device suitable as a power switching device.
2. Discussion of the Background
With receiving demands for miniaturization and high performance of a power equipment in recent power electronics, in the power semiconductor devices, a great deal of efforts have been exerted on improvements of performance for lower power loss, a faster operation speed and higher resistance to breakdown as well as a higher withstand voltage and a larger current flowing through the power semiconductor device. Particularly, to achieve the lower power loss of the semiconductor devices, an ON voltage (constant loss) and a turn-off loss need to be reduced, and various device structures have been developed and investigated. Among these devices, descriptions for a power transistor will be made as a typical middle capacity device used most frequently in a wide field.
FIG.
1
(
a
) and FIG.
1
(
b
) are sectional views showing a constitution of an npn- type power transistor, respectively. FIG.
1
(
b
) is an enlarged view obtained by enlarging an area
24
b
surrounded by dot-dashed lines in FIG.
1
(
a
). In this power transistor, a high concentration n-type collector layer
2
a
is formed on a surface of a high resistance n-type base layer
1
a
. A p-type base layer
3
a
is formed on the other surface of the n-type base layer
1
a
, and an n-type emitter layer
4
a
is selectively formed on a surface of the p-type base layer
3
a
. A base electrode
5
a
is formed on a region of the p-type base layer
3
a
other than that where the n-type emitter layer
4
a
is formed. A collector electrode
6
a
is provided on the n-type collector layer
2
a
, and a source electrode
7
a
is provided on the n-type emitter layer
4
a.
This power transistor operates as follows. It is assumed that a positive voltage is applied to the collector electrode
6
a
and a zero voltage is applied to the emitter electrode
7
a
. At the time the power transistor is turned on, a positive voltage, which has a value larger than that of a built-in voltage of a pn junction composed of the p-type base layer
3
a
and the n-type emitter layer
4
a
, is applied to the base electrode
5
a.
Thus, as shown in
FIG. 2
, holes h are injected from the base electrode
5
a
to the n-type emitter layer
4
a
via the p-type base layer
3
a
, and electrons e are injected from the n-type emitter layer
4
a
to the p-type base layer
3
a
. The electrons e partially disappear by recombining with the holes h in the p-type base layer
3
a
. However, because a junction depth of the p-type base layer
3
a
is formed to be relatively shallow and the collector electrode
6
a
is biased to be a positive potential, the electrons e are injected from the p-type base layer
3
a
to the n-type base layer
1
a
, and pass through the n-type collector layer
2
a
to flow into the collector electrode
6
a.
Furthermore, when the electrons e are injected into the n-type base layer
1
a
, the holes h are also injected into n-type base layer la so as to satisfy a charge neutral condition. By this operation, a conductivity modulation is caused and the power transistor is allowed to be an on-state (conductive state).
On the other hand, at the time the power transistor is turned off, a negative voltage, which has a value smaller than that of a withstand voltage of a pn junction composed of the p-type base layer
3
a
and the n-type emitter layer
4
a
, is applied to the base electrode
5
a
. Upon the application of the negative voltage, a reverse bias is applied between the base and the emitter, thus stopping the electron injection from the n-type emitter layer
4
a
and discharging the holes h stored in the n-type base layer
1
a
from the base electrode
5
a
. As a result, the power transistor is turned off.
Since the conductivity modulation is caused in the n-type base layer
1
a
by injecting the holes h into the n-type base layer
1
a
from the p-type base layer
3
a
in this power transistor, the power transistor has a feature of that an on-voltage is low and a large current can be controlled. However, in the conventional power transistor, a considerable amount of the hole current injected from the base electrode
5
a
in its on-state is not injected into the n-type base layer
1
a
, but recombines with the electrons e within the p-type base layer
3
a
and in the surface of the p-type base layer
3
a
or flows directly into the n-type emitter layer
4
a
via the p-type base layer
3
a.
Similarly, a considerable amount of the electron current injected from the emitter electrode
7
a
is not injected into the n-type base layer
1
a
, but recombines with the holes h within the p-type base layer
3
a
and in the surface of the p-type base layer
3
a
or flows directly into the baser electrode
5
a
via the p-type base layer
3
a.
Therefore, there is a problem that a large base current is required and a current gain (direct current amplification coefficient: h FE=IC/IB) is small. Particularly, in the conventional structure, the p-type base layer
3
a
is formed over the entire of the device effective region except for the junction end portion and the boding pad region for obtaining a main withstand voltage. Here, because a carrier lifetime becomes shorter as impurity concentration becomes higher, the amount of the carrier recombination in the p-type base layer
3
a
becomes very large in the conventional structure in which the p-type base layer
3
a
is formed on the entire of the device effective region. As a result, a current gain is reduced.
As described above, because the current gain is small in the conventional transistor, Darlington-connected two transistors are used. Thus, though the base current may be small, a base current does not flow from the upper stage transistor to the lower stage transistor, if the collector voltage becomes about 0.8 V or more. For this reason, as shown in the current-voltage characteristic of
FIG. 4
, there is a matter that the on-voltage of the device cannot be reduced to 0.8 V or less.
As described above, in the conventional semiconductor device, there is a matter that the current gain is small, or a matter that the on-voltage is large.
SUMMARY OF THE INVENTION
The present invention was made to solve the foregoing problems, and it is an object of the invention to provide a semiconductor device having a trench gate, which is capable of increasing a channel region density and achieving low device resistance.
The present invention was made in consideration of the foregoing matters, and it is an object of the invention to provide a semiconductor device which is capable of increasing a current gain and reducing an on-voltage than conventional semiconductor device.
To achieve the foregoing object, a power transistor according to the present invention comprises: a base layer of a first conductivity type; a collector layer of the first conductivity type formed on one surface of the base layer of the first conductivity type; a first base layer of a second conductivity type selectively formed on the other surface of the base layer of the first conductivity type; and a second base layer of the second conductivity type selectively formed on the other surface of the base layer of the first conductivity type.
The base layer of the second conductivity type is formed dividedly from each other and each of the base layers of the second conductivity type is separated from each other by the base layer of the first conductivity type.
Furthermore, the power transistor according to the present invention is characterized in that an emitter layer of the first conductivity type is arran

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