Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-08-28
2003-04-22
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S566000, C257S573000, C257S584000, C257S593000
Reexamination Certificate
active
06552429
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device suitable for controlling a large current, and more particularly, it relates to an improvement for suppressing oscillation appearing on the potential of a control electrode of a switching element.
2. Description of the Background Art
FIG. 28
is a plan sectional view showing a base portion of a conventional semiconductor device
150
forming the background of the present invention. This semiconductor device
150
is formed as a power module comprising a plurality of power semiconductor elements. As shown in
FIG. 28
, the semiconductor device
150
comprises a substrate
62
on its bottom potion. A plurality of wiring patterns
81
to
85
isolated from each other are arranged on the main surface of the substrate
62
in the form of islands. Two IGBTs
63
and two diodes
64
belonging to an upper arm
70
are arranged on the wiring pattern
81
, while two IGBTs
63
and two diodes
64
belonging to a lower arm
71
are arranged on the wiring pattern
82
.
The four IGBTs
63
and the four diodes
64
are formed as bare chips. Thus, collector electrodes of the two IGBTs
63
and cathodes of the two diodes
64
belonging to the upper arm
70
are electrically connected with each other through the wiring pattern
81
. Similarly, collector electrodes of the two IGBTs
63
and cathodes of the two diodes
64
belonging to the lower arm
71
are electrically connected with each other through the wiring pattern
82
.
A number of conductor wires
75
connect emitter electrodes of the two IGBTs
63
belonging to the upper arm
70
with the wiring pattern
82
. A number of conductor wires
76
connect anodes of the two diodes
64
belonging to the upper arm
70
with the wiring pattern
82
. Similarly, a number of conductor wires
75
connect emitter electrodes of the two IGBTs
63
belonging to the lower arm
71
with the wiring pattern
83
. Further, a number of conductor wires
76
connect anodes of the two diodes
64
belonging to the lower arm
71
with the wiring pattern
83
.
FIG. 28
omits illustration of the conductor wires
75
as the upper arm
70
while omitting illustration of the conductor wires
76
as to the lower arm
71
, in order to avoid complication.
Conductor wires
77
connect the wiring pattern
84
with gate electrodes of the two IGBTs
63
belonging to the upper arm
70
. Similarly, conductor wires
77
connect the wiring pattern
85
with gate electrodes of the two IGBTs
63
belonging to the lower arm
71
.
An external terminal CC supplied with a high power supply potential, an external terminal EE supplied with a low power supply potential, an external terminal OUT connected with a load and external terminals G
1
, G
2
, S
1
and S
2
connected with drive circuits are connected to the wiring patterns
81
to
85
.
FIG. 16
shows connection parts between the wiring patterns
81
to
85
and the external terminals CC, EE, OUT, G
1
, G
2
, S
1
and S
2
with hatching.
In the semiconductor device
150
, as hereinabove described, the serially connected upper and lower arms
70
and
71
are interposed between the high power supply potential and the low power supply potential so that the two IGBTs
63
belonging to the upper arm
70
(and the lower arm
71
) are turned on/off in response to a drive signal input in the external terminal G
1
(and G
2
).
As shown in the example of the semiconductor device
150
, a plurality of power switching elements are connected in parallel with each other in a power module having a large rated current of at least 100 A, for example, in order to share the large current. When unexpected short-circuiting is caused on a load, however, a short-circuit current of about five to 10 times the rated current flows in the power module. In the power module comprising a plurality of power switching elements, the potential of a control electrode (gate electrode in an IGBT) of each switching element may oscillate when such a short-circuit current flows. Such a tendency is recognized that oscillation readily takes place as the rated current of the power module is increased.
Moreover, even in the case when only one switching element is installed on each of the upper arm and lower arm, if the main electrode of a switching element has a plurality of bonding pads (a plurality of belt shape portions indicated in the IGBT
63
in
FIG. 28
) divided into respective sections, the same oscillation tends to occur in the event of a short-circuiting current flowing through it.
Such oscillation may influence normal operation of an applied apparatus utilizing the power module, or cause noise. If the switching element is an IGBT, further, influence on a gate insulator film is also supposed.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a semiconductor device capable of suppressing oscillation appearing on the potential of a control electrode of a switching element.
According to a first aspect of the present invention, a semiconductor device comprises a substrate having a main surface, a first wiring pattern arranged on the main surface, a plurality of switching elements arranged on the first wiring pattern so that first main electrodes thereof are electrically connected with each other, a second wiring pattern arranged on the main surface, a plurality of first conductor wires having first ends connected to second main electrodes of the plurality of switching elements and second ends connected to the second wiring pattern, an external terminal connected to the second wiring pattern for electrically connecting the second main electrodes of the plurality of switching elements with the exterior through the second wiring pattern and a conductor electrically connecting the second main electrodes of the plurality of switching elements with each other without through the second wiring pattern.
In the semiconductor device according to the first aspect, the second main electrodes of the plurality of switching elements connected in parallel with each other are electrically connected with each other through the conductor not relaying the second wiring pattern, i.e., the conductor not fed with a main current, whereby the potentials of the second main electrodes are uniformized between the plurality of switching elements. Consequently, the potentials of control electrodes of the plurality of switching elements are inhibited from oscillation also when a load on the plurality of switching elements is short-circuited.
According to a second aspect of the present invention, the conductor includes a third wiring pattern arranged on the main surface isolatedly from the second wiring pattern and a plurality of second conductor wires having first ends connected to the second main electrodes of the plurality of switching elements and second ends connected to the third wiring pattern.
In the semiconductor device according to the second aspect, electrical connection between the second main electrodes of the plurality of switching elements is readily implemented through the third wiring pattern and the second conductor wires. Further, no wire cutting may be performed on the switching elements in a step of arranging the second conductor wires, to require no means for preventing damage of the switching elements.
According to a third aspect of the present invention, the second wiring pattern extends along the direction of arrangement of the plurality of switching elements, and the third wiring pattern extends along the direction of arrangement of the plurality of switching elements on the side opposite to the second wiring pattern through the plurality of switching elements.
In the semiconductor device according to the third aspect, the second and third wiring patterns are arranged on opposite sides of the plurality of switching elements and extend along the direction of arrangement of the plurality of switching elements, whereby the first and second conductor wires can be readily arranged without interfering with each other. Further, inductive cou
Arai Kiyoshi
Honda Nobuhisa
Matsumoto Hideo
Ho Tu-Tu
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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