Power-switching semiconductor device

Details Power-switching semiconductor device Power-switching semiconductor device

2001-02-27

2003-12-02

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

With extended latchup current level

C257S107000, C257S152000, C257S153000

Reexamination Certificate

active

06657239

ABSTRACT:

TECHNICAL FIELD
The present invention relates to improvement on a power switching semiconductor device such as a gate turn-off thyristor (hereinafter referred to as “GTO”), for example, which has a first main electrode divided into a plurality of segments and a control electrode surrounding the segments formed on a front major surface of a semiconductor substrate, and a second main electrode formed on a rear major surface thereof, respectively, and which performs a turn-on operation between the first main electrode and the second main electrode with a control signal inputted from the control electrode.
BACKGROUND ART
A conventional power switching semiconductor device of this kind will be described with reference to a schematic view of GTO shown in FIG.
4
.
FIG. 4
is a drawing of a semiconductor substrate viewed from a front major surface thereof.
A thyristor having a self arc-extinction capability such as GTO requires a structure endurable against a reverse bias at a turn-off, dissimilar to a common thyristor and a P base layer corresponding to a gate is formed in a mesa structure to achieve a withstand voltage of tens of volts. Cathode electrodes
1
(hereinafter referred to as “segments”) of respective small thyristors each independently fabricated in a mesa structure are arranged radially and in a concentric double ring shape amounting to hundreds to thousands of pieces. A gate electrode
2
constituting a control electrode is formed on a front major surface
3
a
of a semiconductor substrate
3
in such a manner to surround the outer periphery of the segments
1
.
Note that a first main electrode
4
is constituted by connecting the segments
1
.
Further, an anode electrode
5
constituting a second main electrode is formed on a rear major surface
3
b
of the semiconductor substrate
3
.
The following relations was established between an inner segment row
6
forming an inner concentric circle and an outer segment row
7
arranged in a circle concentric to and outside the inner concentric circle:
0
<B
2
≦&agr;
2
×A
2
&agr;
2
≧1.8
(
D
2
−C
2
)/2≦&bgr;
2
×A
2
&bgr;
2
≧1.8
where A
2
is a width of a segment in a circumferential direction, B
2
a distance between adjacent segments in a circumferential direction, C
2
an outer diameter of the inner segment row, and D
2
an inner diameter of the outer segment row.
In the GTO fabricated in such a structure, it is well known to perform the turn-on and turn-off operations, but there has been a problem that a turn-on time is long and a switching action is slow.
The present invention has been made in light of conventional circumstances as described above, and it is accordingly an object of the present invention is to provide a power switching semiconductor device having a shorter turn-on time at a low cost without deteriorating the conventional characteristics.
DISCLOSURE OF THE INVENTION
The present invention is directed to a power switching semiconductor device, in which a first main electrode divided into a plurality of segments forming segment rows of a multi-concentric circle and a control electrode surrounding the segments are formed on a front major surface of a semiconductor substrate, and a second main electrode is formed on a rear major surface thereof, and a turn-on operation is performed between the first main electrode and the second main electrode with a control signal inputted from the control electrode, wherein a turn-on time is reduced without adopting any special structure by specifying a relationship among the maximum width of a segment in a circumferential direction, the minimum distance between adjacent segments in a circumferential direction arrangement, an outer diameter of an inner segment row, and an inner diameter of an outer segment row.


REFERENCES:
patent: 4542398 (1985-09-01), Yatsuo et al.
patent: 4626888 (1986-12-01), Nagano et al.
patent: 4843449 (1989-06-01), Jaecklin et al.
patent: 4910573 (1990-03-01), Roggwiller
patent: 62-184759 (1987-11-01), None
patent: 6-204460 (1994-07-01), None

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