Power switching circuit with reduced interference radiation

Details Power switching circuit with reduced interference radiation Power switching circuit with reduced interference radiation

1999-08-12

2001-11-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S350000, C327S424000, C327S108000

Reexamination Certificate

active

06313689

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a power switching circuit with reduced interference radiation having one or more MOS power transistors.
MOS output stages which form a part of integrated MOS power switching circuits such as, for example, switches or bridge circuits, enable large voltages and currents to be switched with very short rise times and a virtually ideal square-wave shape. However, higher-order spectral components containing those signals in many cases act as interference radiation which affects adjacent electrical or electronic devices and can impair their functioning. For that reason, the possibilities for using such MOS output stages are frequently limited for lack of their electromagnetic compatibility (EMC).
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a power switching circuit with reduced interference radiation, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which has one or more MOS power transistors that enables particularly reliable and effective suppression of instances of interference radiation, particularly during rapid switching processes, in conjunction with a low outlay for circuitry.
With the foregoing and other objects in view there is provided, in accordance with the invention, a power switching circuit with reduced interference radiation, comprising at least one MOS power transistor; and a drive circuit connected to one or at least one MOS power transistor, the drive circuit having a divider for dividing a difference between a maximum output voltage of the at least one MOS power transistor and an instantaneous output voltage at the at least one MOS power transistor as a dividend, by the maximum output voltage of the at least one MOS power transistor as a divisor, to produce a quotient; and a level converter for generating a drive voltage proportional to the quotient for driving the at least one MOS power transistor.
With the objects of the invention in view there is also provided a power switching circuit with reduced interference radiation, comprising at least one pair of low-side and high-side MOS power transistors; a load resistor connected between the MOS power transistors; and a first drive circuit connected to one or at least one low-side MOS power transistor, the first drive circuit having a divider for dividing a difference between a maximum output voltage of the at least one low-side MOS power transistor and an instantaneous output voltage at the load resistor as a dividend, by the maximum output voltage of the at least one low-side MOS power transistor as a divisor, to produce a quotient; and a level converter for generating a drive voltage proportional to the quotient for driving the at least one low-side MOS power transistor.
The invention is based on the fact that particularly effective suppression of interfering harmonic components is possible in MOS power switching circuits when the circuit “recognizes” the extent to which the instantaneous output voltage (V
tx
or V
out
) of the relevant power transistor has approximated the maximum output voltage (V
s
, generally the supply voltage), in order to regulate back the drive voltage (V
a
) proportionally to the difference between those two voltages.
However, the absolute difference is not critical in that case since, given the same difference, for example in the case of a high maximum output voltage (V
s
), the instantaneous output voltage (V
tx
or V
out
) is nearer in terms of percentage to the maximum output voltage than in the case of a lower maximum output voltage. Therefore, a signal is only suitable for regulating back the drive voltage (V
a
) of an MOS transistor when it is related to the maximum output voltage (V
s
). In other words, it is proportional in accordance with the following formula:
V
a
~(
V
s
−V
tx
)/
V
s
.
In the case of push-pull and bridge circuits having at least one pair of low-side and high-side MOS power transistors, between which a load resistor is connected, the following formula {1} holds true for the low-side transistor or transistors:
V
a
~(
V
s
−bV
out
)/
V
s
,
where “Vout” is the output voltage at the load resistor and the factors “a” and “b” may have values in the region of 0.5, 1 or 2.
With V
tx
=V
s
−V
out
, the following formula {2} holds true for the high-side transistor or transistors:
V
a
~aV
out
/bV
s
,
where the factors “a” and “b” may again have values in the region of 0.5, 1 or 2.
The solutions according to the invention described above make use of this insight in that the gates of the MOS transistors are charged and discharged in a defined manner in order to produce “rounded” output characteristic curves in this way, with which the harmonic components are significantly smaller.
In accordance with another feature of the invention, one or at least one of the high-side MOS power transistors may be connected to a second drive circuit in which the divider is provided for dividing an instantaneous output voltage (V
out
) at the load resistor (L) (as a dividend) by the maximum output voltage (V
s
) of the MOS power transistor (as a divisor).
In accordance with a further feature of the invention, the divider is preferably constructed as a first and a second element for logarithmizing the dividend and the divisor, a subtractor for subtracting the logarithmized values, and the level converter connected thereto and having an exponential element for generating the quotient.
In accordance with an added feature of the invention, the first and second elements may be respective first and second diodes, on which a first and a second current is respectively impressed, wherein the currents are in each case proportional to the output voltages to be divided.
In accordance with an additional feature of the invention, the first current is preferably generated through the use of a first resistor to which the supply voltage (V
s
) is applied, a second resistor to which the output voltage (V
out
) is applied, and a transistor differential stage connected to these resistors, while the second current may be generated through the use of a third resistor to which the supply voltage (V
s
) is applied.
In accordance with yet another feature of the invention, the subtractor preferably includes an operational amplifier having a non-inverting input to which a voltage dropped across the first diode is applied and an inverting input to which a voltage dropped across the second diode is applied.
In accordance with yet a further feature of the invention, the maximum output voltage is a supply voltage.
In accordance with yet an added feature of the invention, the dividend is a difference between the maximum output voltage and the instantaneous output voltage multiplied by a predetermined factor.
In accordance with a concomitant feature of the invention, the factor has a value of 0.5, 1 or 2.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a power switching circuit with reduced interference radiation, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 4094186 (1978-06-01), Wessel
patent: 4473759 (1984-09-01), Mahabadi
patent: 4540893 (1985-09-01), Bloomer
patent: 5194760 (1993-03-01), Braun et al.
patent: 5214316 (1993-05-01), Nagai
patent: 5336943 (1994-08-01), Kelly et al.
patent: 5894234 (1999-04-01), Morris
patent: 0508171A1 (1992-10-01), None

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