Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-01-11
2003-03-25
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C363S016000, C363S021010
Reexamination Certificate
active
06538419
ABSTRACT:
The invention relates to a power supply having a burst mode operation and a run mode operation.
BACKGROUND
A typical switch mode power supply (SMPS) includes a switching transistor coupled to a primary winding of power transferring transformer for periodically applying an input supply voltage to the primary winding. It is known to operate the SMPS in a run mode of operation and in a stand-by mode of operation. During a run mode operation, pulses of current are developed in a secondary winding of the transformer at a high frequency and are rectified for periodically replenishing a charge in a filter or smoothing capacitor. An output supply voltage, developed in the capacitor, is connected to energize a load.
In the run mode of operation, the SMPS operates in a continuous mode. In the standby mode of operation, it may be desirable to operate the SMPS in a burst mode for reducing power dissipation. In a given cycle of the burst mode, the high frequency current pulses are developed in the transformer windings. The current pulses are followed by a relatively long interval, referred to herein as dead time interval, of several milliseconds, in which no current pulse is produced.
An on/off control signal may be generated in a microprocessor. The microprocessor is referenced to a potential referred to as cold ground that is conductively isolated from a mains supply voltage. Whereas, a control circuit of the SMPS may include a portion that is conductively non-isolated from the mains supply voltage. The transformer forms a conductive isolation barrier.
It may be desirable to avoid the need for using an additional isolation barrier to apply on/off control information from the conductively isolated microprocessor to the non-isolated SMPS control circuit for changing between the continuous and burst modes.
An advantageous type of a SMPS is a zero voltage switching SMPS. In zero voltage switching SMPS, switching on the transistor occurs when the voltage between the main current conducting terminals of the transistor is zero for minimizing switching losses. It may be desirable to operate the zero voltage switching SMPS in the burst mode, during standby.
In a zero voltage switching SMPS, embodying an inventive feature, the standby mode is initiated by disconnecting a run mode load from the filter capacitor via a switch. Thereby, the run mode load ceases consuming load current. Because the run mode load circuit is de-energized, a feedback loop of the SMPS causes the transistor to conduct in a substantially shorter duty cycle than in the run mode. The short duty cycle in successive switching cycles of the transistor causes the zero voltage switching SMPS to operate in a standby, burst mode.
A transition from the burst mode to the run mode operation is initiated by coupling the run mode load to the filter capacitor via the switch. The increased load current is sensed and results in an increased duty cycle in the transistor. The increased duty cycle causes the zero voltage switching SMPS to operate in the continuous, run mode. Thus, advantageously, the need for using an additional isolation barrier for changing between the continuous and burst modes is avoided.
The filter capacitor voltage may be used for energizing the microprocessor, during the standby mode. It may be desirable to prevent a significant decrease in the capacitor voltage, during a transition interval from the burst mode to the run mode operation. Preventing the discharge of the filter capacitor avoids a possible malfunction. For example, the microprocessor might, disadvantageously, cease operation if its supply voltage were to decrease excessively.
A user may issue a power-on command via, for example, a remote control arrangement. If the switch that couples the run load to the capacitor were to be turned on, during the dead time interval, the capacitor voltage could, undesirably, excessively decrease. This is so because current pulses are not produced.
In carrying out an inventive feature, in response to a user issued power on command, the microprocessor generates a synchronized on/off control signal for turning on the switch. The switch is turned on immediately after the end of the dead time interval for coupling the run mode load to the filter capacitor in synchronization with the end of the dead time interval.
During the dead time interval, when current pulses are not produced, the run mode load is de-coupled from the filter capacitor. Therefore, advantageously, the filter capacitor is not excessively discharged. The result is that, advantageously, the supply voltage does not decrease, during the dead time interval. Furthermore, each current pulse that occurs immediately after the dead time interval replenishes the charge in the filter capacitor.
Assume, for example, that the increase in load current is not sufficient to disable the burst mode operation in a first attempt. The microprocessor will, advantageously, cause the switch to be turned off for the duration of the following dead time interval. As a result, discharging the filter capacitor is, advantageously, prevented. At the end of the dead time interval that follows the first attempt, the microprocessor will cause the switch to be turned on in a second attempt. At that time, the load current may be sufficiently high so that the burst mode operation ceases and the continuous run mode begins.
SUMMARY
A switch mode power supply, embodying an inventive feature includes an output stage for generating output supply pulses in a run mode of operation and in a first portion of a burst mode cycle, during standby mode of operation. The output supply pulses are disabled, during a second portion of the burst mode cycle. A control signal indicative of the occurrence of one of the first and second portions of the burst mode cycle and an on/off signal are generated. A switch responsive to the on/off signal and to the control signal and coupled to the output stage selectively energizes a run mode load circuit at a predetermined time in a burst mode cycle, during a transition between the standby and the run modes of operation.
REFERENCES:
patent: 4734771 (1988-03-01), Lendaro et al.
patent: 4766528 (1988-08-01), Marinus
patent: 4937728 (1990-06-01), Leonard
patent: 5126930 (1992-06-01), Ahn
patent: 5291356 (1994-03-01), Wu
patent: 5390100 (1995-02-01), Palata
patent: 5689407 (1997-11-01), Marinus et al.
patent: 5812383 (1998-09-01), Majid et al.
patent: 5835361 (1998-11-01), Fitzgerald
patent: 5877946 (1999-03-01), Fitzgerald
patent: 6127815 (2000-10-01), Wilcox
patent: 6166926 (2000-12-01), Nath et al.
patent: 0525652 (1996-11-01), None
patent: 0521419 (1998-12-01), None
U.S. Patent Application Ser. No. 09/327,064, filed June 7, 1999 -Arrangement Having a Switched-Mode Power Supply and a Microprocessor M. Rehm et al.
Allen Rick Carl
McPeak Sean Patrick
Nath Gautam
Stevens Joseph Curt
Fried Harvey D.
Han Jessica
Henig Sammy S.
Thomson Licensing S.A.
Tripoli Joseph S.
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