Electrical transmission or interconnection systems – Plural load circuit systems – Selectively connected or controlled load circuits
Reexamination Certificate
2002-01-22
2003-09-02
Riley, Shawn (Department: 2838)
Electrical transmission or interconnection systems
Plural load circuit systems
Selectively connected or controlled load circuits
C363S091000
Reexamination Certificate
active
06614131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switched mode power supply.
2. Description of the Related Art
The general present tendency to reduce the sizes of the electronic devices requires power supplies that produce a low voltage that is stable and precise and will have a small size and good efficiency. Among such types of power supplies are those so-called in switched mode (switched mode power supplies). Shown in
FIG. 1
is a typical power supply that comprises a circuit
100
with a primary winding
101
of a transformer and with a respective input voltage Vin, and which further comprises three circuits
200
,
300
and
400
, each provided with a secondary winding
201
,
301
,
401
of the transformer and producing an output voltage Vo
1
, Vo
2
, Vo
3
at the terminals of a respective load. The main output Vo
1
of the circuit
200
is regulated by a fixed frequency PWM controller
102
, which is placed in feedback between the output Vo
1
and the circuit
100
provided with the primary winding. The PWM controller
102
regulates the output voltage Vo
1
with respect to each change of the input voltage Vin and to each change of a load LD, while as regard to the output voltages Vo
2
and Vo
3
, each change of the input voltage Vin is regulated by the action of the PWM controller
102
, but the changes of the loads relating to the voltages Vo
2
and Vo
3
are not considered by the PWM controller because the circuits
300
,
400
are in open loop configuration with respect to the circuit
100
. Post regulators
302
,
402
, as, for example, linear regulators, DC/DC converters, magnetic amplifiers (mag-amps), are necessary to regulate the voltages Vo
2
and Vo
3
with respect to the changes of the load.
The linear regulators represent a simple and easy-to-design solution. However they present a low efficiency, and for this reason they are utilized above all in low current applications.
The DC/DC converters can be an efficient solution because they allow a good regulation of the output voltage. However they show considerable drawbacks due to the cost of the DC/DC converter, which includes power switches, inductors, capacitors and controllers. Also the DC/DC converter generates added noise and added disturbances which require added filters.
The magnetic amplifiers can be considered as post regulators provided with a programmable delay switch. In fact the magnetic amplifiers have the capability to block some volt/second values of the input voltage to provide a smaller output duty-cycle than the input duty-cycle. The blocked volt/second value depends on the magnetic amplifier feedback loop that controls the output voltage by resetting the saturable core. The magnetic amplifiers generally comprise a reactor provided with a magnetic core and with a control circuit able to reset the magnetic core.
A typical application of a magnetic amplifier consists of a multi-output forward converter shown in
FIG. 2
(which includes a portion of the circuit of FIG.
1
), where the primary
101
of the transformer, which receives in input the voltage Vin, is placed in series to a switch MOS M
1
at the gate terminal of which a voltage signal is present, which is the output voltage Vo
1
of the circuit
200
comprising the secondary winding
201
of the transformer, which is regulated by the fixed frequency PWM controller
102
. A second circuit
24
, which is similar to one of the circuits
300
or
400
of
FIG. 1
, comprises a secondary winding
25
of the transformer, a reactor
26
provided with a magnetic core and connected to the winding
25
and to the anode of a diode D
1
; the cathode of the diode D
1
is connected to the cathode of a diode D
2
placed in parallel to a filter LC and which has the anode connected to the secondary winding
25
. A control circuit
27
is connected to the common terminal of the inductance L and of the capacitor C of the filter LC and it is coupled to the anode of the diode D
1
by means of another diode D
3
placed so that its cathode is connected to the anode of the diode D
1
. The voltage signal VD
2
present at the terminals of the diode D
2
is a pulse width modulated waveform which provides a continuous output signal Vo. The pulse width of the signal VD
2
is controlled by the duty-cycle of the switch MOS M
1
and by the saturable reactor
26
. When the reactor
26
is in an unsaturated state (off state) it blocks the voltage Vs
1
at the terminals of the secondary winding
25
, while, when the reactor
26
is in a saturated state (on state), it shows a low impedance and therefore it blocks a small part of the voltage Vs
1
.
In
FIG. 3
the time diagrams of the voltages and currents associated with the line of the circuit of
FIG. 2
for the continuous inductor conduction mode (CCM) are shown; the voltage Vs
1
at the terminals of the secondary winding
25
, the voltage Vs
2
between the anode of the diode D
1
and ground, the voltage Vma which is the difference between the voltages Vs
1
and Vs
2
, the voltage VD
2
at the terminals of the diode D
2
and the current IL at the terminals of the inductance L of the filter LC are shown. The time periods ton
1
and toff
1
are the switching periods of the MOS switch M
1
, while the period Ts is the whole switching period. The time period tb is the time period during which the reactor is in off state and therefore in such period the magnetic amplifier blocks a volt/second value equal to an area B. The time period during which the reactor
26
is in on state is ton
2
, and in such time period the voltage VD
2
at the terminals of the diode D
2
is high and therefore the current IL rises. During the period tr the reactor
26
is reset by the control circuit
27
. The reset area A is equivalent to the area B.
In
FIG. 4
the time diagrams of the voltages Vs
1
, Vs
2
, Vma, Vd
2
, and of the current IL which are associated with the lines of the circuit of
FIG. 2
for a discontinuous inductor conduction mode (DCM) are shown; the considerations made for the case of the continuous inductor conduction mode are still valid. However, in this case, a positive voltage equal to Vdo appears at the terminals of the diode D
2
during the dead time td during which the current IL in the inductor L is zero. Also, in the DCM conduction case, the time tb is longer than that in the CCM case; this is due to the fact that in the DCM case more stresses are in the reactor
26
than in the CCM case.
In
FIG. 5A
the control circuit
27
is shown in more detail in the case wherein the control circuit
27
implements a voltage reset. Such circuit
27
comprises a pnp transistor Q
1
the emitter terminal of which is coupled to a positive supply voltage Vcc+ and the collector terminal of which is coupled to a negative supply voltage Vcc−. The base terminal of a second npn transistor Q
2
is connected to the collector terminal which has the collector terminal connected to ground and the emitter terminal connected to the anode of the diode D
3
. The current that flows through the transistor Q
1
is controlled by means of an operational amplifier
50
which compares the output voltage Vo of the circuit
24
with a reference voltage VRef. Any variations of the output voltage Vo with respect to the reference voltage VRef causes a variation of the signal driving the transistor Q
1
, and it determines a change of a reset current Ir. The change of the reset current Ir causes a change of the volt/second value of the area B, causing a regulation of the output voltage Vo. The loop gain of the voltage reset circuit is approximately unity. The block Comp is configured to stabilize the system.
In
FIG. 5B
the time diagrams of the voltage Vs
2
and of the reset current Ir, which are relative to the circuit of
FIG. 5A
, are shown.
In
FIG. 6A
the control circuit
27
of
FIG. 2
is shown in more detail in the case wherein such circuit implements a current reset. Such configurations differs from the circuit configuration of
FIG. 5A
because a pnp transistor Q
6
having the emitter terminal co
Lentini Franco
Librizzi Fabrizio
Riley Shawn
Seed IP Law Group PLLC
Tarleton E. Russell
LandOfFree
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