Electrical transmission or interconnection systems – Plural load circuit systems – Plural sources of supply
Patent
1996-07-12
1999-11-23
Paladini, Albert W.
Electrical transmission or interconnection systems
Plural load circuit systems
Plural sources of supply
307 28, 307130, 323229, 327493, H02J 338
Patent
active
059905760
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a power supply voltage supplying circuit wherein power supply voltage is supplied to at least two circuits of different respective operating voltages, and, in particular, it relates to a power supply voltage supplying circuit wherein latch-up is avoided while yet keeping current consumption and electromagnetic interference (EMI) at a low level.
BACKGROUND ART
Conventionally, as a power supply circuit for supplying power supply voltage to two circuits of respectively different operating voltages, the circuit shown in FIG. 4 is known.
In the power supply supplying circuit shown in FIG. 4, voltage V38 and voltage V39 (V38>V39) are respectively supplied from voltage source 32 to a first circuit 38 of operating voltage V38 and a second circuit 39 of operating voltage V39; in this conventional power supply circuit, the construction is such that the ground potential (negative potential) of voltage source 32 that is supplied to first circuit 38 and second circuit 39 is supplied to first circuit 38 and second circuit 39 in common through terminal 37, and the positive potential of voltage source 32 is supplied to the positive potential side of the first circuit through terminal 35 directly, and is supplied to the positive potential side of the second circuit through terminal 36 with a prescribed voltage drop by a Schottky barrier diode 33.
If the potential of terminal 35 is V35, the potential of terminal 36 is V36 and the potential of terminal 37 is V37, V35=V38, V36=V39 and V37=0.
First circuit 38 and second circuit 39 can be regarded as respectively different LSI chips, the operating voltages of first circuit 38 and second circuit 39 being respectively set for example to 4 V and 3.2 V.
In this case, Schottky barrier diode 33 creates a potential difference of 4-3.2=0.8 (V).
Schottky barrier diode 34 is a protective diode. In the drawings, the protective diode is shown with parentheses.
Line 40 is an interface connecting line that connects the first circuit 38 and second circuit 39.
However, the conventional power supply voltage supplying circuit described above is subject to the inconvenience that, since operating voltage V38 of first circuit 38 and operating voltage V39 of second circuit 39 are different and the operating voltage V38 of the first circuit 38 is higher than the operating voltage V39 of second circuit 39, latch-up of the second circuit 39 occurs due to the high level signal input to second circuit 39 through interface connection line 40 from first circuit 38.
FIG. 5 is a view given in explanation of this latch-up phenomenon; in FIG. 5, circuit 48 corresponds to second circuit 39 shown in FIG. 4.
Circuit 48 is supplied with operating voltage Vcc from terminal 41 and has applied to it input signal IN from terminal 42.
Also, circuit 48 is provided with a protective diode 45 connected between LSI chip 47 and terminals 41 and 42 and a protective diode 46 connected between terminal 42 and ground.
When the difference between voltage VIN of input signal IN and operating voltage Vcc exceeds the threshold value Vs of protective diode 45, i.e. when VIN-Vcc>Vs, the current of the input signal IN flows through protective diode 45 as shown by arrow 43 and latch-up occurs.
The latch-up phenomenon can also occur if the voltage VIN of the input signal IN is less by a certain value than the ground potential, with the result that protective diode 46 is turned on and current flows in the direction of arrow 44.
For the above reasons, in the conventional power supply voltage supplying circuit shown in FIG. 4, latch-up occurs if V38-V39>Vs.
As a means for preventing this latch-up phenomenon, as shown in FIG. 6, consideration has been given to providing a level-converting buffer 50 on the interface connection line 40 that connects first circuit 38 and second circuit 39, the difference in levels between the operating voltage V38 of first circuit 38 and operating voltage V39 of second circuit 39 being absorbed by this level-converting buffer 50; however, with this
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Fujii Hironori
Ishii Takaaki
Sakai Masaki
Kabushiki Kaisha Toshiba
Paladini Albert W.
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