Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter
Reexamination Certificate
2001-12-13
2003-09-23
Nguyen, Matthew V. (Department: 2838)
Electric power conversion systems
Current conversion
Including d.c.-a.c.-d.c. converter
Reexamination Certificate
active
06625043
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a switching power supply unit and a driving method thereof, and in particular to a synchronous rectification switching power supply unit that uses switch elements in an output rectifier and a driving method thereof.
Conventionally, a so-called DC-to-DC converter is known as a switching power supply unit. A representative DC-to-DC converter converts a direct current (DC) into an alternating current (AC) by using a switching circuit, transforms (steps up/down) the AC by using a transformer, and converts the resulting AC into a DC by using an output circuit, thereby obtaining a DC output having a voltage different from the input voltage.
In some cases, an output rectifier used in a DC-to-DC converter employs a switch element such as a transistor for control in synchronization with an input switching circuit. ADC-to-DC converter having such an output rectifier is generally called a synchronous rectification switching power supply unit.
FIG. 1
is a circuit diagram showing a general synchronous rectification switching power supply unit.
As shown in
FIG. 1
, a synchronous rectification switching power supply unit includes: a transformer
2
where a primary winding is connected to a positive terminal of a DC input supply
1
; a first transistor
3
connected between a negative terminal of the DC input supply
1
and the primary winding of the transformer
2
; an input capacitor
4
connected across the terminals of the DC input supply
1
; an output rectifier
7
having a second transistor
5
and a third transistor
6
, the output rectifier rectifying waveforms that appear at a secondary winding of the transformer
2
; an output smoothing section
10
having a choke coil
8
and a smoothing capacitor
9
, the output smoothing section smoothing the output of the output rectifier
7
; a control circuit
11
for generating a control signal C based on the output voltage Vo; timing adjusters
12
through
14
for respectively providing the control signal C with predetermined delays; a buffer
15
for generating a first gate signal Vg
1
supplied to the gate of the first transistor
3
based on the output of the timing adjuster
12
; a buffer
16
for generating a second gate signal Vg
2
supplied to the gate of the second transistor
5
based on the output of the timing adjuster
13
; and an inverter
17
for generating a third gate signal Vg
3
supplied to the gate of the third transistor
6
based on the output of the timing adjuster
14
. The output of the output smoothing section
10
is connected to a load
18
to be driven.
FIG. 2
is a timing chart showing a conventional art driving method in the aforementioned synchronous rectification switching power supply unit.
In a synchronous rectification switching power supply unit of this kind, the first transistor
3
and the third transistor
6
alternately repeats turning on and turning off. The basic operation is to turn ON the second transistor
5
while the first transistor
3
is ON.
As shown in
FIG. 2
, in the conventional driving method, to shift the first transistor
3
from OFF to ON and shift the third transistor
6
from ON to OFF, the third gate signal Vg
3
is driven low to turn OFF the third transistor
6
(time t
0
), the first gate signal Vg
1
is driven high to turn ON the first transistor
3
(time t
1
), and finally the second gate signal Vg
2
is driven high to turn ON the second transistor
5
(time t
2
) To shift the first transistor
3
from ON to OFF and shift the third transistor
6
from OFF to ON, the second gate signal Vg
2
is driven low to turn OFF the second transistor
5
(time t
3
), the first gate signal Vg
1
is driven low to turn OFF the first transistor
3
(time t
4
), and finally the third gate signal Vg
3
is driven high to turn ON the third transistor
6
(time t
5
).
In this way, delay amount of each of the timing adjusters
12
through
14
is set so that the timings of the first to third gate signals Vg
1
through Vg
3
are provided as mentioned earlier. By setting the delay amount of the timing adjusters
12
through
14
and changing the first to third gate signals Vg
1
through Vg
3
with the timings shown in
FIG. 2
, it is possible to prevent the first transistor
3
and the third transistor
6
from turning ON simultaneously and causing a through current to flow.
FIG. 7
is a circuit diagram showing a general synchronous rectification switching power supply unit where current mode control is performed.
As shown in
FIG. 7
, a synchronous rectification switching power supply unit includes: a transformer
102
where a primary winding is connected to a positive terminal of a DC input supply
101
; a first transistor
103
and a resistor
120
connected between a negative terminal of the DC input supply
101
and the primary winding of the transformer
102
; an input capacitor
104
connected across the terminals of the DC input supply
101
; an output rectifier
107
having a second transistor
105
and a third transistor
106
, the output rectifier rectifying waveforms that appear at a secondary winding of the transformer
102
; an output smoothing section
110
having a choke coil
108
and a smoothing capacitor
109
, the output smoothing section smoothing the output of the output rectifier
107
; a control circuit
111
for generating a control signal C based on the output voltage Vo; timing adjusters
112
through
114
for respectively providing the control signal C with predetermined delays; a buffer
115
for generating a first gate signal Vg
1
supplied to the gate of the first transistor
103
based on the output of the timing adjuster
112
; a buffer
116
for generating a second gate signal Vg
2
supplied to the gate of the second transistor
105
based on the output of the timing adjuster
113
, and an inverter
117
for generating a third gate signal Vg
3
supplied to the gate of the third transistor
106
based on the output of the timing adjuster
114
. The output of the output smoothing section
110
is connected to a load
118
to be driven.
The resistor
120
is used to extract a current iFET
1
flowing the first transistor
103
as a voltage value. The extracted voltage value is supplied to the control circuit
111
as a current signal S.
FIG. 8
is a timing chart showing a method for generating a control signal C.
As shown in
FIG. 8
, in the control circuit
111
, the output voltage Vo is compared with the current signal S and the control signal C is asserted in response to an internal clock. The control signal C is negated with the timing the value of the current signal S has reached the output voltage Vo. Accordingly, the duty cycle of the control signal C is controlled based on the output voltage Vo and the current signal S. A method for setting the duty cycle of the control signal C based on the comparison between the output voltage Vo and the current signal S is generally called “current mode control.”
In the synchronous rectification switching power supply unit shown in FIG.
1
and driven by the driving method shown in
FIG. 2
, in case the load
18
is light and the output current Io is small, a choke current iL may be inverted in a period the first transistor
3
is OFF (from time t
5
to next time T
0
), as shown in FIG.
2
. In this case, the inverted current flows via the third transistor
6
that is ON. When the third transistor
6
turns OFF at time t
0
, the current flow is interrupted and appears as a fly-back voltage across the third transistor
6
, as shown in FIG.
2
.
Such a fly-back voltage depends on the energy accumulated in the choke coil
8
and may exceed the withstand voltage of the third transistor
6
thus damaging an element. In order to prevent this, it was necessary to use a transistor having a sufficiently high withstand voltage as the third transistor
6
in the related art.
The Japanese Patent Publication No. H11-289760 shows a technology to suppress an inverted current by detecting or predicting the occurrence of an inverted current as an approach to prevent occurrence o
Hatta Masaharu
Shimizu Katsuhiko
Watanabe Masato
Nguyen Matthew V.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
TDK Corporation
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