Power supply switching circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307571, 365226, H03K 301, H03K 17687

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active

049888943

ABSTRACT:
A power supply switching circuit includes first to third MOS transistors (P1, P2 and P3) connected in series between a high-potential source and a standard-potential source. The circuit performs a switching operation using a standard-potential and at least one potential which is different from the standard-poential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2). The back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via turned-off transistor (P1) due to the action of a parasitic diode in the first and second transistors caused by potential fluctuations.

REFERENCES:
patent: 3936676 (1976-02-01), Fujita
patent: 4441172 (1984-04-01), Ebel
patent: 4616143 (1986-10-01), Miyamoto
patent: 4658156 (1987-04-01), Hashimoto
D. Novosel, et al., A 1Mb CMOS EPROM With Enhanced Verificiation, "1988 IEEE International Solid State Circuits Conference", Feb. 1988, pp. 124-125.
S. Tanaka, et al., A Programmable 256K CMOS EPROM With ON-Chip Test Circuits, "1984 IEEE International Solid State Circuits Conference", pp. 148-149.

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