Power supply rejection characteristics of CMOS circuits

Pulse or digital communications – Repeaters – Testing

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307304, 357 42, 357 84, H01L 2704, H01L 2978, H04L 300

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044425295

ABSTRACT:
In a conventional CMOS integrated circuit such as a switched capacitor filter, power supply noise signals are coupled from the substrate to high impedance nodes via various parasitic capacitances. To minimize these noise signals and thereby improve the power supply rejection ratio of the circuit, only N-channel transistors are coupled to the nodes. Additionally, the P-tubs of these transistors are connected to an on-chip regulated power supply. Moreover, for certain metallic runners and capacitors of the circuit that are connected to the specified nodes and parasitically coupled to the substrate, grounded P-tubs are formed directly under the runners and capacitors.

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RCA COS/MOS Digital Integrated Circuits, Databook #SSD-203, (RCA, Somerville, NJ, 1972) pp. 13, 45, 83; CD4000, 4012, 4019.
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McCreary, IEEE J. of Solid State Circuits, vol. SC 10 No. 6, Dec. 1975, pp. 371-379.
Electronic Design, Jun. 7, 1980, pp. 109-123.

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