Power supply monitoring integrated circuit device and...

Details Power supply monitoring integrated circuit device and... Power supply monitoring integrated circuit device and...

1999-07-22

2001-01-09

Wong, Peter S. (Department: 2838)

Electricity: battery or capacitor charging or discharging

Battery or cell discharging

Regulated discharging

C320S134000, C320S118000, C324S433000

Reexamination Certificate

active

06172485

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a power supply monitoring integrated circuit device (hereafter a “power supply monitoring IC”) for monitoring the voltage of a lithium-ion battery or the like so as to control discharging and charging of the battery.
BACKGROUND ART
A conventional power supply monitoring IC will be described with reference to
FIGS. 4 and 5
.
FIG. 4
is a circuit diagram of a lithium-ion power supply apparatus (hereafter a “battery pack”)
1
b
for controlling discharging and charging of three-stage lithium-ion cells
5
to
7
. The lithium-ion cells
5
to
7
, if brought into an overdischarged state, suffer deterioration of characteristics, and therefore the battery pack
1
b,
by the use of a power supply monitoring IC
2
b,
monitors the voltage of the individual cells
5
to
7
to prevent them from being brought into an overdischarged state.
The cells
5
to
7
are connected in series in this order from the highest potential end. The higher potential end of the cell
5
is connected to a detection input terminal U
1
of the power supply monitoring IC
2
b
and to a positive terminal
3
of the battery pack
1
b.
The lower potential end of the cell
7
is connected to an input terminal U
4
and to the drain of an N-channel MOSFET (metal-oxide semiconductor field-effect transistor)
8
.
The source of the MOSFET
8
is connected to the negative terminal
4
of the battery pack
1
b.
The gate of the MOSFET
8
is connected to a terminal T
1
, and, via this terminal T
1
, the MOSFET
8
receives an ON/OFF control signal from the power supply monitoring IC
2
b.
The node between the cells
5
and
6
is connected to an input terminal U
2
. The node between the cells
6
and
7
is connected to an input terminal U
3
.
Within the power supply monitoring IC
2
b,
resistors R
1
and R
2
are connected in series between the terminals U
1
and U
2
. Similarly, resistors R
3
and R
4
are connected in series between the terminals U
2
and U
3
, and resistors R
5
and R
6
are connected in series between the terminals U
3
and U
4
. The terminal U
4
is connected to ground.
The node between the resistors R
1
and R
2
is connected to the non-inverting input terminal (+) of a comparator
11
. To the inverting input terminal (−) of the comparator
11
, a voltage higher than the voltage at the terminal U
2
by a reference voltage Va is fed. The node between the resistors R
3
and R
4
is connected to the non-inverting input terminal (+) of a comparator
12
. To the inverting input terminal (−) of the comparator
12
, a voltage higher than the voltage at the terminal U
3
by a reference voltage Vb is fed. The node between the resistors R
5
and R
6
is connected to the non-inverting input terminal (+) of a comparator
13
. To the inverting input terminal (−) of the comparator
13
, a voltage higher than the ground voltage by a reference voltage Vc is fed. The values of the reference voltages Va, Vb, and Vc are identical.
The outputs of the comparators
11
to
13
are fed to an AND circuit
9
b.
The AND circuit
9
b
outputs a logical product signal SD, which is fed to an overdischarge control circuit
10
. In accordance with this signal SD, the overdischarge control circuit
10
turns on and off the MOSFET
8
, which is connected to the terminal T
1
.
The comparators
11
to
13
individually check whether the voltages of the cells
5
to
7
are higher than a predetermined overdischarge voltage or not. The overdischarge voltage is set, for example, at 2.2 V. If the voltages of all of the cells
5
to
7
are higher than the overdischarge voltage, the AND circuit
9
b
outputs a high level as the signal SD. By contrast, if the voltage of any of the cells
5
to
7
is lower than the overdischarge voltage, the AND circuit
9
b
outputs a low level as the signal SD.
When the signal SD is at a high level, the overdischarge control circuit
10
keeps the MOSFET
8
on so that electric power is supplied to the device (not shown), such as a personal computer, connected to the terminals
3
and
4
. By contrast, when the signal SD turns to a low level, the overdischarge control circuit
10
turns off the MOSFET
8
to inhibit the discharging of the cells
5
to
7
.
FIG. 5
shows another example of a conventional battery pack
1
c
having a configuration different from that of the conventional battery pack (
FIG. 4
) described above. Here, for cells
5
to
7
, a plurality of detection circuits
30
to
32
are used in combination. The detection circuits
30
to
32
are configured identically, and are formed, for example, within a single integrated circuit.
Within each of the detection circuits
30
to
32
, resistors R
1
and R
2
are connected in series between terminals U
1
and U
2
. The node between the resistors R
1
and R
2
is connected to the non-inverting input terminal (+) of a comparator
35
. To the inverting input terminal (−) of the comparator
35
, a voltage higher than the voltage at the terminal U
2
by a reference voltage Va is fed. The result of the comparison performed by the comparator
35
is fed out via a terminal T
0
.
The signals output via the terminal T
0
of the individual detection circuits
30
to
32
are fed to an AND circuit
36
. In response, the AND circuit
36
outputs a signal SD, which is fed to an overdischarge control circuit
34
. When the signal SD is at a high level, the overdischarge control circuit
34
keeps a MOSFET
8
on; by contrast, when the signal SD turns to a low level, the overdischarge control circuit
34
turns off the MOSFET
8
. In this way, the same overdischarge control is achieved as achieved by the circuit shown in FIG.
4
. Note that, in
FIG. 5
, such elements as are found also in
FIG. 4
are identified with the same reference numerals and symbols, and overlapping descriptions will not be repeated.
However, in the first conventional example, the power supply monitoring IC
2
b
(
FIG. 3
) can only cope with three-stage cells
5
to
7
. That is, different power supply monitoring ICs are required to cope with different numbers of stages of cells. This means that different power supply monitoring ICs need to be manufactured for different numbers of stages of cells. This complicates management of power supply monitoring ICs and the like, and lengthens the time required for evaluation, designing, and the like of battery packs and the like.
On the other hand, the second conventional example permits flexible connection in accordance with the number of stages of cells, as shown in FIG.
5
. However, to perform an AND operation on the signals output from the detection circuits
30
to
32
, it is necessary to use an additional component
33
that needs to be mounted separately. This demands extra costs.
DISCLOSURE OF THE INVENTION
An object of the present invention is to provide a power supply monitoring IC that can control different numbers of cells without requiring any separately-mounted component or the like, and to provide a battery pack employing such a power supply monitoring IC.
To achieve the above object, in one configuration according to the present invention, a power supply monitoring IC, having input terminals for receiving the voltages of a plurality of cells and a plurality of comparing means for comparing the voltages of the individual cells with a predetermined reference voltage, for controlling discharging or charging of the cells in accordance with the outputs of the comparing means is characterized by being provided with a mode terminal for receiving a signal for designating the number of cells that are controlled by the power supply monitoring IC, a first circuit that can forcibly bring part of the comparing means into a predetermined output state in accordance with the signal received at the mode terminal, and a second circuit for excluding from monitoring the outputs of those comparing means which have been brought into the predetermined output state.
According to this configuration, the power supply monitoring IC compares the volt

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