Power supply insensitive substrate bias voltage detector...

Details Power supply insensitive substrate bias voltage detector... Power supply insensitive substrate bias voltage detector...

1998-09-24

2001-01-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000

Reexamination Certificate

active

06172554

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to providing voltages.
2. Description of Related Art
Voltage generating circuits are widely used in electrical and electronic devices. For instance, substrate bias generator circuits, also referred to as back-bias generators, are used in semiconductor devices which require the substrate region to be biased to a predetermined voltage. For example, in dynamic random access memories (DRAM) the substrate region is negatively biased to prevent the DRAM cells from losing the stored information. The back-bias generator includes a voltage multiplier circuit, commonly referred to as charge pump, for providing the negative Back-Bias Voltage (V
BB
). The charge pump is usually accompanied by a V
BB
detector circuit. The detector circuit regulates the charge pump such that V
BB
is maintained as close to a target V
BB
value as possible.
The detector circuit constantly senses the V
BB
voltage level, and if V
BB
becomes more negative than the target V
BB
, the detector circuit turns off the charge pump thereby allowing V
BB
to drift back to the target V
BB
; and if V
BB
becomes less negative than the target V
BB
, the detector circuit turns on the charge pump to pump V
BB
back to the target V
BB
.
FIG. 1
shows a conventional V
BB
detector circuit
17
. Serially connected resistors R
1
and R
2
are coupled between the power supply Vcc and V
BB
terminal
15
. Vcc is provided by a power supply external to the device, and V
BB
is generated internally by a charge pump (not shown). Inverter
12
has its input terminal connected to node
11
which is the node between R
1
and R
2
. The output terminal of inverter
12
also provides the output terminal Q
10
of the detector circuit
17
. Output terminal Q
10
is connected to the charge pump.
Vcc, R
1
, R
2
, and V
BB
form a voltage divider which sets the voltage V
A
at node
11
in accordance with the following equation:
V
A
=[(R
2
×
Vcc
)+(R
1
×
V
BB
)]/(R
1
+R
2
)  (1)
Resistors R
1
and R
2
are selected so that, for the nominal Vcc value and target V
BB
, the voltage V
A
equals the trip point of inverter
12
. If the charge pump causes V
BB
to become more negative than the target value, V
A
drops below the trip point of inverter
12
causing Q
10
to go high. The high level at Q
10
turns off the charge pump, allowing V
BB
to increase back to the target value. Alternatively, if V
BB
becomes less negative than the target V
BB
, V
A
rises above the trip point of inverter
12
causing Q
10
to go low. The low level of Q
10
turns on the charge pump causing V
BB
to become more negative. Thus, V
BB
is maintained at the target value.
Circuit
17
however, suffers from a number of drawbacks, one of which is that V
BB
varies with changes in Vcc. In particular, as shown by equation (1), if Vcc increases, V
BB
has to become more negative to keep V
A
at the trip point of inverter
12
(this assumes that inverter
12
is designed so that its trip point is insensitive to Vcc). This increases junction leakage as explained in more detail below. The increased junction leakage adversely impacts the operation of the device. For example, in a DRAM the increased junction leakage can cause loss of information stored in the memory cells; and more generally, the high leakage current results in higher static power consumption, e.g., high stand-by current (I
SB
).
As both Vcc and |V
BB
| increase, leakage current increases across the junction between Vcc-biased n+ diffusion regions in the V
BB
-biased P-type substrate. This is more clearly illustrated in FIG.
2
.
FIG. 2
shows a P-type substrate
23
biased to V
BB
through the p+ diffusion region
22
. The n+ diffusion region
21
represents one of many n+ diffusion regions biased to Vcc. The pn junction formed by the P-substrate
23
and the n+ diffusion
21
is reverse biased since a positive voltage Vcc is applied to the negatively charged n+ diffusion
21
and a negative voltage V
BB
is applied to the positively charged P-type substrate
23
.
In accordance with the I-V characteristics of a pn junction, as the reverse voltage across the pn junction approaches the junction break down voltage (V
BD
), larger leakage current flows through the junction. Therefore, an increase in Vcc and the resulting more negative V
BB
, combine to cause a greater reverse voltage across the junction formed by the n+ region
21
and substrate
23
.
The undesirable effects of the large leakage currents, such as high I
SB
and data loss in DRAM cells, are magnified as technology moves to smaller geometries and memory devices move to higher densities.
Another drawback of circuit
17
(
FIG. 1
) is that it does not prevent V
BB
from becoming positive. If V
BB
becomes positive by as little as 0.8V, junctions formed by Vss-biased n+ regions and the V
BB
-biased substrate become forward biased. This can lead to latch-up which may destroy the device.
FIG. 3A
shows a prior art detector circuit
37
which prevents V
BB
from becoming positive. Circuit
37
is identical to circuit
17
of
FIG. 1
except that NMOS transistor M
30
is connected between node
11
and R
2
. With the gate of M
30
connected to Vss, M
30
turns off when its source (lead
33
) reaches minus one threshold voltage (−V
TN
), V
TN
being that of M
30
. When M
30
turns off, V
A
rises to Vcc. This causes the charge pump to turn on and pump V
BB
to a more negative voltage.
It is desirable to provide an improved V
BB
detector.
SUMMARY
The inventors have observed that it is sometimes desirable to obtain V
BB
values closer to 0V than those provided by the V
BB
detector of FIG.
3
A. The V
BB
range for circuit
37
(
FIG. 3A
) is illustrated in FIG.
3
B. The horizontal axis represents Vcc and the vertical axis represents V
BB
. The threshold voltage V
TN
is that of M
30
which is typically about 1V. Voltage V
X
represents the upper limit to which the charge pump may pump V
BB
(the upper limit typically equals the junction breakdown voltage V
BD
). The region bounded by −V
TN
and −V
X
(shown as the cross-hatched region) represents the V
BB
voltage range which circuit
37
tolerates. Given the technology trend towards smaller geometries and the above-mentioned problems caused by the increased junction leakage, lower V
BB
target values in the range of −1V to 0V (e.g. −0.5V) are highly desirable.
Accordingly, a V
BB
detector circuit is needed wherein V
BB
is made insensitive to Vcc variations, and also the range of possible V
BB
values is increased without compromising power consumption.
In some embodiments of the present invention, a voltage is provided which is substantially insensitive to power supply voltage variations. In some embodiments, the voltage is a bias voltage V
BB
. The substantial insensitivity to the power supply voltage variations is achieved in some embodiments by using a detector circuit which generates a signal substantially insensitive to power supply voltage variations. For example, in some detector circuit embodiments, the resistor R
1
of
FIG. 1
is replaced by a current source. The current provided by the current source is substantially insensitive to power supply voltage variations. As a result, the voltage on node
11
is substantially insensitive to power supply voltage variations. In some embodiments, the inverter
12
is also made substantially insensitive to power supply voltage variations. Therefore, V
BB
becomes substantially insensitive to power supply voltage variations.
Some embodiments of the present invention allow a voltage generated by a voltage generating circuit to get arbitrarily close to 0 volts while still not allowing the voltage to become positive. Thus, some V
BB
generators include a circuit that allows V
BB
to get arbitrarily close to 0 volts but does not allow V
BB
to become positive. In some embodiments, this is achieved by biasing the gate of transistor M
30
of
FIG. 3A
to the th

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