Power supply device with reduced power consumption

Details Power supply device with reduced power consumption Power supply device with reduced power consumption

2003-01-23

2004-11-16

Nguyen, Matthew V. (Department: 2838)

Static information storage and retrieval

Powering

Conservation of power

C365S185230, C365S226000

Reexamination Certificate

active

06819620

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a power supply device for a flash memory, and more particularly, to a power supply device with reduced power consumption.
2. Description of the Prior Art
Recently, flash memory technology has quickly developed owing to a great demand for portable electric products. The flash memory related market is also further advancing associated research into flash memory devices. The portable electric products include digital cameras, cellular phones, video game apparatuses, personal digital assistants, electric recorders, and programmable ICs. For example, digital cameras need the flash memory to replace traditional film, and cellular phones, video game apparatuses, personal digital assistants, electric recorders, and programmable ICs require the flash memory to store data or programs.
The flash memory is a non-volatile memory. That is, the flash memory records data through changing a threshold voltage of a transistor or a memory cell to control a gate channel induced at the transistor or the memory cell. The data stored in the flash memory, therefore, will not be cleared or lost even though a corresponding operating voltage of the flash memory is turned off. The flash memory is viewed as a special structure of an electrically erasable and programmable read only memory (EEPROM). In other words, the flash memory alters the number of electrons stored on a floating gate to affect the corresponding threshold voltage. For the sake of programming the EEPROM, a Flowler-Nordheim tunneling mechanism or a hot electron injection mechanism, generally speaking, is used to control the number of electrons stored on the floating gate. Therefore, if the number of electrons is decreased, the corresponding threshold voltage is lowered. The binary value “0” is accordingly recorded by the flash memory. On the other hand, if the number of electrons is increased, the corresponding threshold voltage is raised. The binary value “1” is accordingly recorded by the flash memory.
Please refer to
FIG. 1
, which is a schematic diagram of a prior art flash memory device
10
. The flash memory device
10
has a controller
11
, a memory
12
, a sense amplifier
14
, a page buffer
16
, a driving circuit
18
, and a power supply device
20
. The controller
11
is used to output a control signal to control operation of the flash memory device
10
. The memory
12
has a plurality of memory blocks
22
wherein each memory block
22
has a plurality of memory cells
24
. The memory cells
24
are arranged in a matrix format for individually storing binary values. In addition, each memory block
22
has a plurality of transistors
25
. The memory cell
24
is accessed when the corresponding transistor
25
is turned on. The memory cell
24
, as mentioned above, records one binary value “1” or “0” according to the number of electrons stored on the floating gate. When a driving voltage is applied to the memory cell
24
for turning on the memory cell
24
, the driving voltage has to overcome the threshold voltage that is affected by the number of electrons stored on the floating gate. That is, the number of electrons stored on the floating gate will accordingly affect an output current passing through the memory cell
24
. The sense amplifier
14
is electrically connected to the controller
11
for reading the binary value recorded by the memory cell
24
when receiving the control signal generated from the controller
11
. The sense amplifier
14
is capable of precisely determining the binary value recorded by the memory cell
24
according to either the voltage or the current outputted from the memory cell
24
. The page buffer
16
is electrically connected to the controller
11
, and is capable of driving the memory cells
24
to perform a writing operation so as to store the binary values. The driving circuit
18
has a plurality of decoders
28
for locating the memory cells of the memory block
22
according to the control signal generated from the controller
11
. Each decoder
28
corresponds to one of the memory blocks
22
of the memory
12
. For example, the decoder
28
a
corresponds to the memory block
22
a
, and the decoder
28
b
corresponds to the memory block
22
b
. The decoder
28
includes a plurality of word line drivers
30
individually electrically connected to memory cells
24
that are positioned at the same row in the memory block
22
, and a select gate driver electrically connected to memory cells that are positioned at different columns of the memory block
22
. Therefore, the word line driver
30
and the select gate driver
32
select one memory cell
24
out of the memory block
22
. In addition, the power supply device
20
is used to provide each decoder
28
with appropriate operating voltages, for example, the driving voltages required to turn on the transistors
25
and the memory cells
24
.
Please refer to
FIG. 2
in conjunction with FIG.
3
.
FIG. 2
is a schematic diagram of the power supply device
20
shown in
FIG. 1
, and
FIG. 3
is schematic diagram of the word line driver
30
shown in FIG.
1
. The power supply device
20
includes a plurality of voltage sources
34
for providing different output voltages, and a switch
36
for selecting the output voltages and outputting the selected output voltages from corresponding output terminals A, B, C, D to the driving circuit
18
so as to providing each decoder
28
with the appropriate operating voltages. For instance, if the voltage sources
34
a
,
34
b
,
34
c
,
34
d
,
34
e
respectively generate 7 volts, 3 volts, 1.5 volts, 0 volts, −10 volts, when the decoder
28
a
processes the memory block
22
a
according to the control signal of the controller
11
, each word line driver
30
needs a first driving voltage (0 volts) or a second driving voltage (−10 volts) to control access of memory cells positioned at the same word line in the memory block
22
a
. Therefore, the voltage source
34
e
outputs 10 volts from the output terminal C to word line drivers
30
of the decoder
28
a
with the help of the switch
36
, and the voltage source
34
d
outputs 0 volts from the output terminal D to other word line drivers
30
of the decoder
28
a
with the help of the switch
36
. The target word line is then selected, and the memory cells
24
located at the selected word line are capable of being accessed. As shown in
FIG. 3
, the word line driver
30
can be fabricated by a complementary metal oxide semiconductor (CMOS) transistor process. That is, the word line driver
30
has a plurality of CMOS transistors
38
. The CMOS transistor
38
has a p-channel metal oxide semiconductor (PMOS) transistor
40
electrically connected to the first driving voltage and an n-channel metal oxide semiconductor (NMOS) transistor
42
electrically connected to the second driving voltage. Please note that only one transistor
38
is shown in
FIG. 3
for simplicity. The driving circuit
18
generates a selecting signal according to the control signal outputted from the controller
11
. The selecting signal is used to control operation of word line drivers
30
and the select gate driver
32
of each decoder
28
. If the controller
11
intends to access the memory cells
24
of the memory block
22
a
, the driving circuit
18
will input the selecting signal to the decoder
28
a
after receiving the control signal of the controller
11
. Then, the memory block
22
a
operates under a selected mode. In the meanwhile, another decoder
28
b
will not receive the selecting signal so that the corresponding memory block
22
b
operates under an unselected mode. Therefore, the decoder
28
a
is capable of controlling the word line driver
30
to access memory cells
24
located at each word line of the memory block
22
a
. When the memory cells
24
positioned at the word line N are accessed, the selecting signal keeps the transistor
40
off and turns on the transistor
42
. Therefore, the word line N will approach the second driving voltage (−10

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