Static information storage and retrieval – Powering
Reexamination Certificate
2002-06-05
2004-12-07
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Powering
C365S201000, C365S230030, C714S014000
Reexamination Certificate
active
06829193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power supply control circuit for use in a semiconductor storage device, which can optimize the ability to supply power according to an operation mode in which the semiconductor storage device is placed.
2. Description of the Prior Art
FIG. 12
is a block diagram showing an arrangement of a prior art power supply control circuit for use in a semiconductor storage device (e.g. DRAM), in which an arrangement of a VPP pump circuit with respect to a memory array of the semiconductor storage device is illustrated. In
FIG. 12
, reference numeral
101
denotes a subarray that is a part of the memory array of the semiconductor storage device, reference numeral
102
denotes a row decoder, and reference numeral
103
denotes a VPP pump circuit. In general, the VPP pump circuit consists of a main pump circuit that operates when the semiconductor storage device is activated and a small pump circuit that is mainly used to hold the level of each cell when the semiconductor storage device is on standby. The main pump circuit and the small pump circuit are arranged locally on a chip equipped with the semiconductor storage device.
FIGS. 13A
to
13
C are drawings showing operation modes of the prior art semiconductor storage device. In
FIGS. 13A
to
13
C, since the same reference numerals as shown in
FIG. 12
denote the same components or like components, the explanation of those components will be omitted hereafter. In
FIGS. 13A
to
13
C, reference numeral
104
denotes a selected subarray which is hatched in the figure.
FIG. 13A
shows normal active mode,
FIG. 13B
refreshing mode, and
FIG. 13C
shows test mode (disturbance acceleration test state).
In operation, in the semiconductor storage device, since the number of word lines selected differs according to the operation mode in which the semiconductor storage device is placed, the number of selected subarrays
104
also differs according to the operation mode in which the semiconductor storage device is placed. As a result, the power consumption in the semiconductor storage device differs according to the operation mode in which the semiconductor storage device is placed. For example, as shown in
FIGS. 13A
to
13
C, the ratio among the amounts of power consumption of VPP supplied by the VPP pump circuit
103
at the normal active mode, at the test mode, and at the refreshing mode can be 1:4:8.
When the VPP pump circuit
103
of the semiconductor storage device is designed so that the ability to supply VPP is maximized at the normal active mode and the refreshing mode, the ability to supply VPP is not sufficient at the test mode. If the ability to supply VPP is not sufficient at the test mode, since it takes much time to test the semiconductor storage device and the voltage level of VPP decreases, the frequency of detection of defective pieces will decrease. In contrast, when the VPP pump circuit
103
of the semiconductor storage device is designed so that the ability to supply VPP is maximized at the test mode, the ability to supply VPP becomes excessive and therefore the power consumption increases at the normal active mode and at the refreshing mode.
A problem with a prior art power supply control circuit constructed as mentioned above for use in a semiconductor storage device is that since the power consumption differs according to the operation mode in which the semiconductor storage device is placed, the frequency of detection of defective pieces decreases at the test mode when the ability to supply power is insufficient, whereas the power consumption increases when the ability to supply power becomes excessive.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the above-mentioned problem, and it is therefore an object of the present invention to provide a power supply control circuit for use in a semiconductor storage device, capable of increasing the frequency of detection of defective pieces and stabilizing the power consumption by optimizing the ability to supply power according to the operation mode in which the semiconductor storage device is placed.
In accordance with an aspect of the present invention, there is provided a power supply control circuit for use in a semiconductor storage device, the circuit comprising: a first power supply circuit connected to all subarrays of the semiconductor storage device, for supplying power to all the subarrays; an operation mode determination circuit for determining an operation mode in which the semiconductor storage device is placed and for generating a first block selection signal based on address information applied thereto according to the determined operation mode; a row control circuit disposed for each of all the subarrays, for generating a second block selection signal based on the first block selection signal according to the determined operation mode; and a second power supply circuit disposed for each of all the subarrays, for supplying power to a corresponding one of all the subarrays according to the second block selection signal from a corresponding row control circuit. Accordingly, the power supply control circuit can efficiently supply VPP at the instant, at which the power consumption of VPP is large, following the selection of one or more subarrays, and can also efficiently supply VPP to one or more selected subarrays in which the power consumption of VPP is large. In addition, since even if which any one or more subarrays are selected in either of the operation modes one or more second power supply circuits corresponding to the one or more selected subarrays can thus be activated, the ability to supply VPP can be optimized. Furthermore, since the ability to supply VPP can be optimized according to the operation mode in which the semiconductor storage device is placed, the frequency of detection of defective pieces can be increased and the power consumption can be stabilized.
In accordance with another aspect of the present invention, the operation mode determination circuit includes a selector for generating an internal address based on the address information according to the determined operation mode, and a decoder for generating the first block selection signal based on the internal address generated by the selector according to the determined operation mode.
In accordance with a further aspect of the present invention, the power supply control circuit further comprises a control circuit for outputting a detection signal indicating a voltage level of the power supplied to all the subarrays, and the second power supply circuit supplies the power to the corresponding one of all the subarrays in response to the detection signal from the control circuit while the semiconductor storage device is placed in predetermined operation mode. Accordingly, the power supply control circuit can handle any decrease in the voltage level of VPP which occurs when the semiconductor storage device remains at the predetermined state for a long time.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
REFERENCES:
patent: 6038186 (2000-03-01), Tanizaki
patent: 6385115 (2002-05-01), Nakai
patent: 6551846 (2003-04-01), Furutani et al.
patent: 6731561 (2004-05-01), Abe et al.
patent: 09231754 (1997-09-01), None
Renesas Technology Corp.
Yoha Connie C.
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