Static information storage and retrieval – Powering
Reexamination Certificate
2000-06-27
2001-08-14
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Powering
C365S193000, C365S222000, C365S230030
Reexamination Certificate
active
06275439
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a power supply in a semiconductor device; and, more particularly, to a power supply selectively using a chip driving power and a data input/output driving power in a semiconductor device.
DESCRIPTION OF THE PRIOR ARTS
Generally, in DRAM (dynamic random access memory) device, a power supply applied to the device has been used in driving both the memory chip and data input/output devices without using a separate power supply. However, in synchronous DRAM devices having fast data input/output speed, two power supplies, i.e., first and second power supplies Vcc and Vccq, are employed to supply power to an internal circuit and data input/output devices.
Referring to
FIG. 1
, a conventional power supply includes a first power supply Vcc for driving an internal circuit
110
and a second power supply Vccq for driving a data input/output unit
150
.
However, nevertheless the separate power supply to drive the data input/output is prepared, it is not contributed to the high speed operation, especially in a refresh mode because only the first power supply is used. Accordingly, it is easy to make a noise and many refresh operations are needed.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a power supply control apparatus to increase operation speed in a memory device, by alternatively changing a power line connection type based on an operation mode of a memory device.
It is another object of the present invention to provide a power supply control apparatus to minimize a noise and improve operation speed of a memory device.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device comprising: a switching means for selectively coupling a first power line providing power to an internal circuit to a second power line providing power to a data input/output unit in response to a control signal which is produces according to an operation mode; and a control means for receiving row address strobe signals corresponding to each of memory banks, and a self-refresh signal activated in a refresh mode and producing the control signal.
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Ho Hoai V.
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
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