Power supply configured sensing scheme for flash EEPROM

Details Power supply configured sensing scheme for flash EEPROM Power supply configured sensing scheme for flash EEPROM

1995-05-25

1996-11-05

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

365207, G11C 1134

Patent

active

055724655

ABSTRACT:
Bias selector circuitry for a memory cell sensing circuit is described. The bias selector circuitry includes a reference voltage generator, an output node, and a selector. The output node provides the bias voltage to the reference bitline load and the sense bitline load for controlling the reference and sense bitline node voltages, respectively. The selector provides a first bias voltage to the output node if a power supply voltage is at a first level. The selector selects the reference voltage generator to provide a second bias voltage to the output node if the power supply voltage is at a second level. The reference bitline node voltage is maintained at approximately the midpoint of the operating range of the sense bitline node voltage.

REFERENCES:
patent: 5243573 (1993-09-01), Makihara
patent: 5245574 (1993-09-01), Fray
patent: 5444656 (1995-08-01), Bauer

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