Power supply clamp circuitry for electrostatic discharge (ESD) p

Details Power supply clamp circuitry for electrostatic discharge (ESD) p Power supply clamp circuitry for electrostatic discharge (ESD) p

1998-06-17

1999-12-28

Jackson, Stephen W

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361115, 361118, H02H 900

Patent

active

060089709

ABSTRACT:
Circuitry is provided which increases the efficiency of electrostatic discharge (ESD) power supply clamping circuitry to sink larger currents during an ESD event on a power supply node. Voltage clamp circuits capable of providing ESD protection to a supply node are described. The voltage clamp circuits include a discharge transistor which is controlled by a control circuit during an ESD event. The control circuit operates in response to a voltage provided on the protected supply node. One embodiment provides a P-channel MOS transistor and a control circuit which drives the gate of the transistor. Another embodiment provides an N-channel MOS transistor and a control circuit which drives the gate of the transistor.

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Grove, A., Physics and Technology of Semiconductor Devices, John Wiley & Sons, Pubs., New York, Book cover and copyright information provided, p. 323, (1967).
Merrill, R., et al., "ESD Design Methodology", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 6 pages, (Sep. 28-30, 199).
Wann, C., et al., "High-Performance 0.07-um CMOS with 9.5-ps Gate Delay and 150 GHx ft", IEEE Electron Device Letters, vol. 18, No. 12, pp. 625-627, (Dec. 1997).
Worley, E.R., et al., "Sub-Micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions", EOS/ESD Symposium, 9 pages, (Sep. 1995).

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