Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-30
2004-12-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185130
Reexamination Certificate
active
06829168
ABSTRACT:
FIELD OF THE INVENTION
The present invention broadly relates to an electronic multilevel non-volatile memory device which is monolithically integrated in a semiconductor substrate and includes a circuit structure for data programming. More particularly, the invention relates to a power supply circuit structure for a row decoder of a multilevel non-volatile memory device and the following description is given with specific reference to this field of application just for convenience of illustration.
BACKGROUND OF THE INVENTION
As is well known in this technical field, recent developments in non-volatile memories, particularly in EPROM, EEPROM and Flash-EEPROM memories, provide an increase in storage capacity by employing multilevel architectures, i.e. memory arrays whose cells can store plural logic states. A comparative review of the circuit structures of classic two-level memories may help for a better understanding of the features of this invention.
Electronic memory devices usually comprise at least one array or matrix of memory cells arranged as rows and columns. Logic information can be read/written from/to each cell by biasing a corresponding row and column.
A typical memory cell comprises a field-effect transistor having a control gate terminal, a floating gate region capacitively coupled to the control gate, a source terminal, and a drain terminal. The two possible logic states of a two-level memory cell, e.g. a logic “0” indicating a programmed cell and a logic “1” indicating an erased cell, are separated by a potential range. To discriminate the information contained in a non-volatile two-level memory it is sufficient to compare the current flowing through the memory cell with the current flowing through a reference cell that is similar in structure with the memory cell and has a known threshold voltage.
The operation allowing selection of a cell to read its information content includes applying an appropriate bias voltage to the control gate of the memory cell. If the cell has already been programmed previously, an electric charge will be found trapped in the floating gate region, and the cell threshold voltage will depress the drain current being conducted by the memory cell below that of the reference cell. On the contrary, if the cell was erased, no electric charge will be trapped in the floating gate region, and the cell conducts a drain-source current which is higher than that of the reference cell.
Thus, the most commonly used method of reading from a flash memory cell provides a comparison between the current draw from the cell to be read with the current draw from the reference cell. The comparison is performed in a simple comparator, known as a sense amplifier, which performs the comparison and outputs a corresponding result. The sense amplifier compares the current draw from the cell with the current draw from the reference cell, and accordingly converts the analog information of the addressed data into a digital form.
When a multilevel memory device must be sensed, discriminating the logic values of a cell with an n-bit storage capacity requires no less than 2
n
−1 references that may be voltage-mode or current-mode references according to the reading method implemented. For example, an approach to determining the state of an n-level memory cell is described in U.S. Pat. No. 5,774,395. Unlike a two-level memory, the reference cells of a multilevel memory require additional programming circuitry so that intermediate logic levels can be written in the reference cells for comparison with those logic levels that have been or can be programmed in the memory cell array.
Reliability considerations call for the working range of the threshold voltage to be unrelated to the number of bits contained in the cell. Therefore, the multilevel mode requires that the threshold gap between different distributions be reduced. Reducing the gap between distributions means reducing the current differentials to be detected, and this impacts the degree of accuracy demanded of the sense amplifier.
In addition, since the cell reading phase is carried out by set bias currents, any resistance that may occur in series with the source and drain terminals is bound to occasion a smaller effective gain of the cell, and hence a reduced current dynamic range. Thus, to maintain a current reading mode, all the effects of series resistance should be reduced or minimized, and this is achieved by reading a cell with a number of gate voltages. However, a problem that arises directly from this procedure is that of the row voltage switching time. In general, row voltage is conveyed over the power supply of the row decoder.
Thus, varying the row voltage means varying the power supply of the row decoder or portion thereof. Since the parasitic capacitance that is associated with the row decoder is about hundreds of picoFarads (pF), it will be appreciated that this prior technique expands the reading time to an unacceptable extent.
At present, a standard access time is about a hundred nanoseconds (ns) even for a multilevel memory. Shifting in voltage a capacitance of hundreds of pF with the precision that the multilevel mode requires would extend the reading time by some microseconds (&mgr;s). In an effort to obviate such drawbacks, the state of the art provides a special row decoding structure that comprises a plurality of main row decoders for generating first and second control signals, and a plurality of local row decoders for responding to the first and second control signals with the generation of a wordline selecting signal. This is the structure described, for instance, in the U.S. Pat. No. 6,064,023.
While being advantageous on several counts, the above structure does not prove capable of generating at any particularly high rate the positive and negative voltage values that are needed for programming and erasing the memory cells.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a power supply circuit structure for a row decoder, which can bring the time for switching between the different gate voltages down, such as to the time constant of the array row.
A further object of the invention is that of providing a reading process that is simple, controlled, and highly accurate for reading the reference cells of a multilevel memory.
Another object of the invention is that of keeping the programming time of the reference cells substantially the same for all the array sections.
These and other objects are obtained by providing a plurality of supply voltages to the row decoder, and applying such voltages through conduction paths that are enabled similarly as in a hierarchic decoding. The invention relates to a power supply circuit structure for a row decoder of a multilevel non-volatile memory device including a matrix of memory cells and associated reading and programming circuits, wherein the memory device comprises multiple supply voltages for the row decoder, and a switching circuit or switching means for transferring the voltages through conduction paths that are enabled according to a hierarchic-mode decoding system.
REFERENCES:
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Campardo et al., “40-mm23-V-Only 50 MHz 64-Mb 2-b/cell CHE NOR Flash Memory”, IEEE Journal of Solid-State Circuits, IEEE Inc., New York, US, vol. 35, No. 11, Nov. 2000, pp. 1655-1666, XP-001131052.
Atsumi et al., “A 3.3 V-only 16Mb Flash Memory wirh Row-Decoding Scheme”, Solid-State Circuits Conference, 1996, Digest of Technical Papers. 42ndISSCC 1996 IEEE Int'l San Francisco, CA, Feb. 8, 1996, pp. 42-43, XP-10156390A.
Campardo Giovanni
Micheloni Rino
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Hoang Huan
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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