Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-03-28
2003-12-23
Berhane, Adolf D. (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S315000
Reexamination Certificate
active
06667607
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a power supply circuit, and more particularly, to a power supply circuit used in a charger for portable electronic equipment or the like.
In the prior art, the voltage capacity of devices that configure an internal circuit of an IC chip, which is used in, for example, a charger for electronic portable equipment, is determined by the maximum rating voltage. The IC chip is manufactured in accordance with a manufacturing process that corresponds to the voltage capacity of the devices.
Generally, when a device having a high voltage capacity is used in an IC chip, the area occupied by the device increases. This increases the chip area and causes the manufacturing process to be complicated. Accordingly, the employment of devices having a high voltage capacity increases costs.
When a power supply voltage greater than or equal to the maximum rating voltage is applied to a power supply IC chip, the power supply voltage may damage devices. Thus, devices that have a large voltage capacity must be used to withstand a power supply voltage that is greater than or equal to the maximum rating voltage. However, when the internal devices have a high voltage capacity, the chip area increases, which increases the manufacturing cost.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a power supply circuit that withstands voltages greater than or equal to the voltage capacity and prevents the circuit area from increasing without increasing manufacturing cost.
To achieve the above objective, the present invention provides a power supply circuit including a first transistor for receiving a DC voltage and generating an internal power supply voltage. A clamp circuit is connected to the first transistor. The clamp circuit is activated when the DC current voltage is an excessive voltage to clamp the internal power supply voltage at a predetermined voltage that is less than the excessive voltage. A gate voltage control circuit is connected to the first transistor and the clamp circuit for supplying a gate of the transistor with a control voltage so that the internal power supply voltage decreases when the clamp circuit is activated.
A further perspective of the present invention is a power supply circuit including a p-channel MOS transistor. A first diode, a zener diode, and a first NPN transistor are connected in series between the p-channel MOS transistor and a predetermined power supply. A second NPN transistor has a base connected to a base of the first NPN transistor. A current mirror circuit is connected to the second NPN transistor and the p-channel MOS transistor.
A further perspective of the present invention is a semiconductor device including a power supply circuit. The power supply circuit includes a first transistor for receiving a DC voltage and generating an internal power supply voltage. A clamp circuit is connected to the first transistor. The clamp circuit is activated when the DC current voltage is an excessive voltage and clamps the internal power supply voltage at a predetermined voltage that is less than the excessive voltage. A gate voltage control circuit is connected to the first transistor and the clamp circuit to supply a gate of the transistor with a control voltage so that the internal power supply voltage decreases when the clamp circuit is activated.
A further perspective of the present invention is a semiconductor device including a power supply circuit. The power supply circuit includes a p-channel MOS transistor. A first diode, a zener diode, and a first NPN transistor are connected in series between the p-channel MOS transistor and a predetermined power supply. A second NPN transistor has a base connected to a base of the first NPN transistor. A current mirror circuit is connected to the second NPN transistor and the p-channel MOS transistor.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 4567381 (1986-01-01), Piasecki
patent: 4885484 (1989-12-01), Gray
patent: 5465190 (1995-11-01), Meunier et al.
patent: 5530340 (1996-06-01), Hayakawa et al.
patent: 6078204 (2000-06-01), Cooper et al.
patent: 6222355 (2001-04-01), Ohshima et al.
patent: 6222709 (2001-04-01), Baba
Ito Hidenobu
Kawamura Hiroshi
Nakamichi Hiroto
Shimizu Katsuya
Berhane Adolf D.
Fujitsu Limited
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