Electric lamp and discharge devices: systems – Plural power supplies
Reexamination Certificate
2000-04-04
2001-10-02
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
C345S095000, C323S282000, C323S288000
Reexamination Certificate
active
06297596
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power supply circuits and liquid crystal display devices. More particularly, the present invention relates to a power supply circuit arranged to generate an intermediate voltage and a liquid crystal display device operating according to an output of the power supply circuit.
2. Description of the Background Art
The arrangement of a conventional liquid crystal display device will be described with reference to
FIG. 11. A
liquid crystal display device
4000
shown in
FIG. 11
includes a liquid crystal panel
4500
having pixels arranged in a matrix, a Y driver
4100
to drive the pixels of liquid crystal panel
4500
in the horizontal axis direction, an X driver
4200
to drive the pixels of liquid crystal panel
4500
in the vertical axis direction, a control circuit
4300
to control Y driver
4100
and X driver
4200
, and a power supply circuit
4400
to supply Y driver
4100
and X driver
4200
with a reference power supply voltage for driving.
One example of the power supply circuit will be described with reference to
FIG. 12. A
power supply circuit
900
shown in
FIG. 12
outputs reference power supply voltages through resistor division. Power supply circuit
900
includes resistors R
1
, R
2
, . . . , Rn which are connected in series between a node supplied with a power supplied voltage VEE and a node supplied with a ground voltage GND. Power supply circuit
900
is formed to divide a difference in voltage between power supply voltage VEE and ground voltage GND by bleeder resistors R
1
to Rn and thereby obtain reference power supply voltages (intermediate voltages) V
0
to V
4
, for example.
Another example of the conventional power supply circuit is as shown in
FIG. 13. A
power supply circuit
910
shown in
FIG. 13
includes bleeder resistors R
1
to Rn which are connected in series between a node supplied with power supply voltage VEE and a node supplied with ground voltage GND, and operational amplifiers OA
0
, OA
1
, . . . , OA
4
. Operational amplifiers OA
0
, OA
1
, . . . , OA
4
are generically referred to as operational amplifiers OA.
Power supply circuit
910
divides a voltage which corresponds to a difference between power supply voltage VEE and ground voltage GND by using the resistors, performs impedance conversion through operational amplifiers OA to stabilize each intermediate voltage, and then outputs the intermediate voltages.
Operational amplifier OA includes transistors Q
91
, Q
92
, Q
93
, Q
94
and Q
95
as shown in FIG.
14
. Transistors Q
91
, Q
92
and Q
95
are PMOS transistors while transistors Q
93
and Q
94
are NMOS transistors.
The gate of transistor Q
91
is connected to an inversion input terminal N (corresponding to symbol “−” in FIG.
13
), and the gate of transistor Q
92
is connected to a non-inversion input terminal P (corresponding to symbol “+” in FIG.
13
).
Transistors Q
93
and Q
94
have their sources receiving ground voltage GND. Transistor Q
95
has its gate connected to a bias input terminal BIAS and supplied with a bias voltage. Transistor Q
95
has its source receiving power supply voltage VEE and its drain connected commonly to the sources of transistors Q
91
and Q
92
. Transistor Q
95
serves as a constant current source to supply transistors Q
91
and Q
92
a suitable bias current.
Operational amplifier OA further includes transistors Q
96
and Q
97
and a capacitance element C
0
. Transistor Q
97
is an NMOS transistor while transistor Q
96
is a PMOS transistor. Transistor Q
97
has its gate connected to the drain of transistor Q
94
, its source receiving the ground voltage, and its drain connected to an output terminal OUT.
Transistor Q
96
is connected between a node supplied with power supply voltage VEE and output terminal OUT and has its gate supplied with the bias voltage from bias input terminal BIAS. Transistor Q
96
operates as a constant current source load.
Capacitance element C
0
is connected between the drain and the gate of transistor Q
97
.
In a liquid crystal display device, a larger number of pixels increases load capacitance, and higher impedance of a power supply for driving the liquid crystal causes a noise on a liquid crystal output waveform. When power supply circuit Q
910
is used, degradation in the display quality can be prevented from dropping by attaining lower impedance through operational amplifiers OA.
In any of such conventional power supply circuits, the resistance value of a bleeder resistor is desirably smaller to stabilize a reference power supply voltage. However, a smaller resistance value of the bleeder resistor results in power consumption increase of the power supply circuit.
In power supply circuit Q
910
, if a sufficient power amount is to be obtained for liquid crystal display by using an operational amplifier, the current flowing in a constant current circuit in the operational amplifier has to be made higher to some extent. That substantially prevents lower power consumption.
In order to cope with the problem, Japanese Patent Laying-Open No. 55-146487 (hereinafter, referred to as Document 1) discloses a power supply circuit which can stabilize an output voltage even if the resistance value of a bleeder resistor is made higher.
The power supply circuit arrangement shown in Document 1 will be described with reference to
FIG. 15. A
power supply circuit
920
shown in
FIG. 15
obtains intermediate voltages using higher resistance and detects voltage fluctuation which exceeds an acceptable value to suppress the fluctuation using MOS transistors.
Power supply circuit
920
includes resistors R
1
to R
8
, operational amplifiers OA
1
to PA
4
, transistors Q
1
to Q
4
, and a power supply E. Power supply E is connected between a node Z
0
and a node Z
3
. Resistors R
1
to R
3
are connected in series between nodes Z
0
and Z
3
. Resistors R
1
to R
3
produce intermediate voltages (−V1), (−V2) which are provided by dividing the power supply voltage (−E=−V3) into three.
Resistors R
4
to R
8
are connected in series between nodes Z
0
and Z
3
. Resistors R
4
to R
8
produce reference voltages (−VH1, −VL1, and (−VH2, −VL2), for setting acceptable fluctuation values, based on intermediate voltages (−V1), (−V2) as a center. The following expressions (1) to (4) are satisfied between the reference voltages and the intermediate voltages.
−VH1=−V1+&Dgr;V (1)
−VL1=−V1−&Dgr;V (2)
−VH2=−V2+&Dgr;V (3)
−VL2=−V2−&Dgr;V (4)
In expressions (1) to (4), &Dgr;V represents an acceptable fluctuation value.
Power supply circuit
920
further includes an operational amplifier OA
1
receiving reference voltage (−VH1) at its inversion input terminal (“−”) and voltage (−V1) at its non-inversion input terminal (“+”), and a transistor Q
2
connected between a node Z
1
for outputting voltage (−V1) and node Z
3
for outputting a voltage (−V3) and receiving an output of operational amplifier OA
1
at its gate. Transistor Q
2
is an NMOS transistor. If voltage (−V1) fluctuates and becomes higher than reference voltage (−VH1), transistor Q
2
turns on. Thus, fluctuation in the output so that the output is higher than the acceptable value is suppressed.
Power supply circuit
920
further includes an operational amplifier OA
2
receiving reference voltage (−VL1, at its inversion input terminal (“−”) and voltage (−V1) at its non-inversion input terminal (“+”), and a transistor Q
1
connected between node Z
1
and node Z
0
for outputting a voltage V
0
and receiving an output of operational amplifier OA
2
at its gate. Transistor Q
1
is a PMOS transistor. If voltage (−V1) fluctuates and becomes lower than reference voltage (−VL1), transistor Q
1
turns on. Thus, fluctuation in the output so that the output is lower
Lee Wilson
Sharp Kabushiki Kaisha
Wong Don
LandOfFree
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