Power supply circuit and semiconductor memory

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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C323S284000, C363S060000, C327S536000, C365S226000

Reexamination Certificate

active

07576523

ABSTRACT:
A power supply circuit that outputs a set voltage from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first detecting signal when the voltage outputted from the boosting circuit is not lower than a first detection voltage set lower than the set voltage, and outputs a second detecting signal when the voltage outputted from the boosting circuit is not lower than the set voltage; and a clock signal generating circuit that outputs, based on a reference clock signal, a clock signal and an inverted clock signal obtained by inverting the clock signal, and stops outputs of the clock signal and the inverted clock signal in response to the second detecting signal.

REFERENCES:
patent: 6122185 (2000-09-01), Utsunomiya et al.
patent: 6525949 (2003-02-01), Johnson et al.
patent: 6853566 (2005-02-01), Itoh
patent: 7042275 (2006-05-01), Suwa et al.
patent: 7123067 (2006-10-01), Yasui et al.
patent: 2008/0116963 (2008-05-01), Jung
patent: 2008/0137428 (2008-06-01), Nakai et al.

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