Electricity: power supply or regulation systems – Output level responsive – Using an impedance as the final control device
Reexamination Certificate
2002-09-12
2004-02-10
Berhane, Adolf D. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using an impedance as the final control device
C345S210000
Reexamination Certificate
active
06690149
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a power supply which is included in a display apparatus such as a liquid crystal display apparatus and used for supplying electric power for driving display pixels, and a display apparatus equipped with the power supply.
BACKGROUND OF THE INVENTION
Referring to
FIG. 4
which is an explanatory drawing of the present invention, the following description will discuss a liquid crystal display apparatus which is an example of a display apparatus.
On the side of segment electrodes of a liquid crystal panel
1
, a segment driver
3
for driving segment electrodes X
1
-Xm is provided, while on the side of common electrodes, a common driver
2
for driving common electrodes Y
1
-Yn is provided. To the segment driver
3
, a power supply circuit (power supply)
5
supplies driving electric powers V
0
, V
2
, V
3
, and V
5
. In contrast, to the common driver
2
, the power supply circuit
5
supplies driving electric powers V
0
, V
1
, V
4
, and V
5
.
Various circuit arrangements have conventionally been proposed as the power supply circuit
5
which supplies the driving electric powers V
0
-V
5
. By the way, in the power supply circuit
5
, a generation circuit for supplying voltages to the segment driver
3
is substantially identical with a generation circuit for supplying voltages to the common driver
2
. Therefore the generation circuit for supplying a voltage for the segment driver
3
is taken as an example here, for the sake of simplicity.
For instance, a power supply circuit
35
, which is illustrated in
FIG. 7
, outputs driving electric powers V
0
, V
2
, V
3
, and V
5
by voltage-dividing using resistances. In this power supply circuit
35
, three bleeder resistances R
101
, R
102
, and R
103
divide the voltage between an electric power (VEE) and a ground (GND) so as to generate two intermediate voltages, and these two are outputted as driving electric powers V
2
and V
3
.
In contrast, as illustrated in
FIG. 8
, a power supply circuit
36
is arranged such that lines, which are used for obtaining the driving electric powers V
2
and V
3
by voltage-dividing using resistances in the power supply circuit
35
in
FIG. 7
, are connected with operational amplifiers OP
1
and OP
2
, for dropping the impedance of an output stage. This power supply circuit
36
makes it possible to regulate the driving electric powers V
2
and V
3
generated by way of voltage-dividing, by carrying out impedance conversion in the operational amplifiers OP
1
and OP
2
.
In the power supply circuits
35
and
36
, the values of the bleeder resistances R
101
through R
103
are preferably small, to reduce the voltage fluctuation and to regulate the voltages of the driving electric powers V
0
, V
2
, V
3
, and V
5
, even if pixels of the liquid crystal panel
1
which is a capacity load are charged or discharged. However, when the values of the bleeder resistances R
101
through R
103
are small, the power consumption in the power supply circuits
35
and
36
is high.
Moreover, when the operational amplifiers OP
1
and OP
2
in the power supply circuit
36
obtain enough electric power for liquid crystal displaying, constant currents in the operational amplifiers are high to a certain extent, and this obstructs the reduction of the power consumption. That is, in each of the operational amplifiers OP
1
and OP
2
, constant current sources are mainly provided in (i) a differential pair section in the input stage and (ii) the output stage, and especially the constant current source in the output stage, which is provided as a load circuit, cannot follow the voltage fluctuation if the value of the constant current is low.
To solve the above-identified problem, Japanese Laid-Open Patent Application No. 55-146487/1980 (Tokukaisho 55-146487; published on Nov. 14, 1980) discloses a power supply circuit which is basically arranged similar to the aforementioned power supply circuit
35
but the driving electric powers V
0
, V
2
, V
3
, and V
5
can be regulated despite the values of the bleeder resistances are risen in order to reduce the power consumption.
As
FIG. 9
illustrates, a high voltage side is grounded in a power supply circuit
37
disclosed by the publication above, and thus driving electric powers V
0
, −V
2
, −V
3
, and −V
5
are acquired. The power supply circuit
37
is arranged so that output voltages which are outputted as the driving electric powers −V
2
and −V
3
are generated by bleeder resistances (hereinafter, will be simply referred to as resistances) having high resistance values, and fluctuations surpassing acceptable voltage values of the respective driving electric powers −V
2
and −V
3
are detected so that the fluctuations are restrained by MOS transistors MQ
11
through MQ
14
. Incidentally, DN is an electric power node and SN is a grounding node in FIG.
9
.
In the power supply circuit
37
, series resistances R
101
through R
103
are resistance voltage-dividing circuits, in which a voltage −V
5
of an electric power E is divided in three so that intermediate voltages which are to be the driving electric powers −V
2
and −V
3
are obtained. Then with reference to the divided voltages −V
2
and −V
3
which are intermediate voltages obtained by voltage-dividing using resistances, reference voltages −VH
2
, −VL
2
, −VH
3
, and −VL
3
for setting respective acceptable ranges &Dgr;V of the voltage fluctuations are generated by a voltage dividing circuit constituted by series resistances R
104
-R
108
.
Moreover, a voltage comparator circuit (hereinafter, will be simply referred to as comparator) CMP
1
, whose inverting input terminal receives the reference voltage −VH
2
while non-inverting input terminal receives the divided voltage −V
2
, and an nMOS transistor MQ
12
, which is connected between a divided voltage output point and the voltage −V
5
of the electric power E and controlled by the output of the comparator CMP
1
, are provided, so that when the output voltage of a line through which the divided voltage −V
2
runs varies so as to surpass the reference voltage −VH
2
in the positive direction (towards the ground voltage), the nMOS transistor MQ
12
is turned on in order to restrain the output fluctuation surpassing the acceptable range &Dgr;V in the positive direction.
Meanwhile, (i) a comparator CMP
2
whose non-inverting input terminal receives the reference voltage −VL
2
while inverting input terminal receives the divided voltage −V
2
and (ii) a pMOS transistor MQ
11
, which is connected between the divided voltage output point and the ground voltage V
0
and controlled by the output of the comparator CMP
2
, are provided, so that when the output voltage of a line through which the divided voltage −V
2
runs varies so as to surpass the reference voltage −VL
2
in the negative direction (towards the voltage −V
5
), the pMOS transistor MQ
11
is turned on in order to restrain the output fluctuation surpassing the acceptable range &Dgr;V in the negative direction.
Likewise, the fluctuation of the output voltage −V
3
, which surpasses the acceptable range &Dgr;V, is restrained. That is to say, a comparator CMP
3
, whose inverting input terminal receives the reference voltage −VH
3
while non-inverting input terminal receives the divided voltage −V
3
, and an nMOS transistor MQ
14
, which is connected between the divided voltage output point and the voltage −V
5
of the electric power E and controlled by the output of the comparator CMP
3
, are provided, so that when the output voltage of a line through which the divided voltage −V
3
runs varies so as to surpass the reference voltage −VH
3
in the positive direction (towards the ground voltage), the nMOS transistor MQ
14
is turned on in order to restrain the output fluctuation surpassing the acceptable range &Dgr;V in the positive direction.
In the meantime, (i) a comparator
Katsutani Masafumi
Monomoushi Masahiko
Berhane Adolf D.
Birch & Stewart Kolasch & Birch, LLP
Sharp Kabushiki Kaisha
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