Power-sum circuit for finite field GF(2.sup.m)

Details Power-sum circuit for finite field GF(2.sup.m) Power-sum circuit for finite field GF(2.sup.m)

1997-11-07

1999-08-03

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 700

Patent

active

059318945

ABSTRACT:
A cellular-array power-sum circuit designed to perform AB.sup.2 +C computations in the finite field GF(2.sup.m) is presented, where A, B, and C are arbitrary elements of GF(2.sup.m). This new circuit is made up of m.sup.2 identical cells each consisting of an AND logic unit and an exclusive-OR logic unit. The AND logic unit may be configured to comprise three 2-input AND gates, and the exclusive-OR logic unit may be configured to comprise one 4-input XOR gate. The presented cellular-array power-sum circuit has a computation time of 2m gate delays. It is this power-sum circuit that provides basis for using circuits of pipeline architectures to compute exponentiations, inversions, and divisions in GF(2.sup.m).

REFERENCES:
patent: 4745568 (1988-05-01), Onyszchuk et al.
patent: 5046037 (1991-09-01), Cognault et al.
patent: 5101431 (1992-03-01), Even

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