Power sequencing and ramp rate control circuit

Details Power sequencing and ramp rate control circuit Power sequencing and ramp rate control circuit

2002-12-16

2004-02-17

Vu, Bao Q. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S273000, C323S284000

Reexamination Certificate

active

06693410

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to controlling voltages on power up and in particular the present invention relates to controlling the power sequencing and ramp rate of voltages applied to integrated circuits.
BACKGROUND
With the ongoing decrease in feature size used to design integrated circuits (ICs), it has become common for ICs to require multiple power supplies. For example, a common I/O voltage for digital ICs is either +3.3V or +5V and a common core voltage is in the range of 1.5V to 3.3V. Typically, an IC manufacture requires specific characteristics from the power supplies. Such characteristics include the order in which the power supplies are applied (power sequencing) and the ramp rate of the voltages (i.e. the rate of time in which a power supply ramps up from zero volts to its specified voltage).
Power sequencing is usually accomplished with the use of time delay circuits that control pass devices such as power field effect transistors (FETs) which operate as a switch. For example, a typical time delay circuit includes a current source, a capacitor and the pass device. The current source is adapted to charge a capacitor. When the voltage across the capacitor rises above some fixed reference threshold, the circuit is adapted to turn on the pass device. A desired requirement for a power sequencing application is that the circuit operates reliably from an input voltage of zero volts up to the normal voltage of the power supply. Unfortunately, with the typical implementation of power sequencing circuits utilizing the time delay circuits as described above, both a fixed reference (usually a band-gap device) and a comparator of the power sequencing circuit require a minimum non-zero voltage applied to their power inputs to operate properly. As a result, the typical power sequencing circuit of the prior art as described above is difficult to operate reliably from an input voltage of zero volts (V) to the normal voltage of the power supply. Another common power sequencing application has a similar limitation. In this method time delays are created with the use of an oscillator of a known frequency and a counter adapted to count a given number of clock cycles. However, in this type of power sequencing application, the typical oscillator requires even a higher voltage on its power input before it is operational which makes it impractical for very short delays. What is desired in the art is a power sequencing application that operates reliably all the way down to zero volts and a power sequencing application that is also configured to create very short delays times.
One known method of controlling the ramp rate is by indirectly utilizing a slow-start circuit on the controller of a DC-DC or AC-DC power converter. However, the slow-start circuits are intended to reduce input surge current on power up and are typically not designed to meet the power-up requirements of a specific load. This is typically because the power converters are purchased as modules from a vendor and the circuit designer has little input into the design of the module. In this situation, the best that can be achieved is to select a module which has an output voltage ramp rate that meets the requirements of the integrated circuits used. What is desired in the art is a ramp rate circuit adapted to effectively handle a defined power source. The situation is further complicated when multiple circuits on a circuit board require different (possibly conflicting) power sequencing and voltage ramp rates. In this case, it is impossible to select a module which will meet all of the requirements and additional circuitry required. Accordingly, it is further desired in the art to have a simple circuit to control time delay and ramp control rate.
SUMMARY
The above-mentioned problems and other problems of the prior art are overcome by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a power control circuit is disclosed. The power control circuit comprises a delay resistor, a delay capacitor and an input transistor. The delay resistor is adapted to be coupled to an input power supply. The delay capacitor is coupled in series with the delay resistor. The input transistor has an emitter that is adapted to be coupled to the input power supply through the delay resister. The input transistor conducts current when a voltage across the delay capacitor rises above a selected voltage threshold of the input transistor. A power source is applied to a load in response to the conduction of the input transistor which is delayed by the time it takes to charge the delay capacitor to the selected voltage threshold.
In further another embodiment, another power control circuit is disclosed. This power control circuit includes first and second nodes, a delay resistor, a delay capacitor, an input transistor, an amplifying transistor, a pass device and first and second feedback resistors. The first node is adapted to be coupled to a I/O power supply. The second node is adapted to be coupled to a core power supply. The delay resister is coupled between the delay capacitor and the first node. The input transistor has an emitter that is coupled to the first node through the delay resistor. The amplifying transistor has a base coupled to the collector of the input transistor. The pass device has an activation input that is coupled to a collector of the amplifying transistor. The pass device further has a power input that is coupled to the second node and output adapted to be coupled to a load. The pass device passes the core power supply coupled to the second node to the load when the activation input of the pass device receives a current from the collector of the amplifying transistor. The first feedback resistor is coupled between the output of the load to a base of the input transistor. The second feedback resistor is coupled between the base of the input transistor and a ground.
In another embodiment, a method of operating a power control circuit to regulate the coupling of a power source to a load is disclosed. The method comprises coupling the power source to an emitter of an input transistor through a delay resistor. Coupling the power source to a delay capacitor through the delay resistor. Charging the delay capacitor. When the charge on the delay capacitor exceeds a base-emitter threshold voltage of the input transistor, producing an activation current with the input transistor and then passing the power source to the load in response to activation current.
In yet another embodiment, a method of operating a power control circuit is disclosed. The method comprises coupling a first power source at a first node. Coupling a second power source at a second node. Coupling the first power source to an emitter of an input transistor through a delay resistor. Charging a delay capacitor coupled to the first power source through the delay resistor. Activating the input transistor when the charge on the delay capacitor exceeds an emitter-base voltage threshold of the input transistor and passing the second power source to a load in response to the activation of the input transistor.


REFERENCES:
patent: 5686820 (1997-11-01), Riggio, Jr.
patent: 6184669 (2001-02-01), Matsuo
patent: 6377033 (2002-04-01), Hsu
patent: 6472854 (2002-10-01), Ootani

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