Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-07-12
2004-03-23
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S341000, C257S343000, C257S401000
Reexamination Certificate
active
06710441
ABSTRACT:
TECHNICAL FIELD
This invention relates to power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor.
BACKGROUND OF THE INVENTION
Computational power of digital processing circuitry is related to the conversion of input DC power to waste heat. As digital computational powers increase, the associated power consumption and heat generated by processing devices also increase. Power supply voltages of logic circuits have been reduced from 5 Volts to 1.2 Volts or less to alleviate excessive generation of heat and power consumption. However, reduction of power supply voltages has complicated other issues of power supply and distribution to logic circuits. For example, electrical resistance between power supplies and logic circuits has a more significant impact upon efficiency as supply voltages continued to be reduced.
Some designs have provided power to PC boards at high voltages (e.g., 48 Volts) and then utilize on-board converters to convert the received high voltage energy to 1.2 Volt or other low voltage supply energy for application to logic circuits. To minimize the size of such converters, the stored energy requirements in the magnetics and capacitors can be reduced by increasing the switching frequency of the converter. However, conventional power semiconductor configurations utilized in converters and capable of handling relatively large currents can not typically switch efficiently at the desired switching speeds.
FIG. 1
depicts a conventional vertical geometry power MOSFET device having a plurality of n+ source contact regions
3
which lie within p (body) regions
3
P (typically formed as hexagonal islands), where both the p (body) regions
3
P and the n+ source contact regions
3
are electrically connected to the upper source contact metal
3
M. The gate conductors
2
are insulated from source contact metal
3
M under which they lie by the insulator
3
l
and from the silicon substrate by the thin gate insulator
2
l
. The gate conductors
2
cover the regions between the p (body) regions
3
P, extending across the edge (surface channel) portion of the perimeter of the p (body) regions
3
P to the n+ source regions
3
. When the gate conductors
2
are biased more positively than the threshold voltage of this conventional n-channel power MOSFET, electron flow through these surface channel regions is induced which results in electron flow along indicated paths
4
. Electron paths
4
are formed from the adjacent n+ source regions
3
horizontally through the surface channel, vertically through the n− drain drift region
5
N to the n+ drain region
5
to the bottom drain metallization contact
6
shown in FIG.
1
. This current flow path leads to values of source-drain ON resistance that are higher than desired for efficient low voltage power conversion applications.
The equivalent circuit of a conventional power MOSFET illustrated in
FIG. 1
is depicted in
FIG. 2. A
p-n body diode
7
is provided from the source
3
to the drain
6
and comprises the p body region
3
P and the n− and n+ drain regions
5
N and
5
shown in FIG.
1
. The body diode
7
is a relatively large p-n
−
-n
30
diode with a very large diffusion charge storage capacity Q
d
. Accordingly, when the body diode
7
is first reversed biased after heavy forward conduction, a large transient reverse current j
t
flows for a substantial period of time t
r
=Q
d
/j
t
which can limit usable switching frequencies.
There exists needs for improved semiconductor devices and methodologies which overcome problems associated with conventional arrangements.
REFERENCES:
patent: 4175240 (1979-11-01), Kremlev et al.
patent: 4256977 (1981-03-01), Hendrickson
patent: 4462041 (1984-07-01), Glenn
patent: 4710349 (1987-12-01), Yamazaki et al.
patent: 4794441 (1988-12-01), Sugawara et al.
patent: 4955790 (1990-09-01), Nakanishi et al.
patent: 5038194 (1991-08-01), Takahama
patent: 5143865 (1992-09-01), Hideshima et al.
patent: 5148064 (1992-09-01), Kevorkian et al.
patent: 5298797 (1994-03-01), Redl
patent: 5470795 (1995-11-01), Shushurin
patent: 5479089 (1995-12-01), Lee
patent: 5479117 (1995-12-01), Gabara
patent: 5493275 (1996-02-01), Easter
patent: 5532179 (1996-07-01), Chang et al.
patent: 5548150 (1996-08-01), Omura et al.
patent: 5608616 (1997-03-01), Umeda et al.
patent: 5652183 (1997-07-01), Fujii
patent: 5726872 (1998-03-01), Vinciarelli et al.
patent: 5728594 (1998-03-01), Efland et al.
patent: 5736766 (1998-04-01), Efland et al.
patent: 5744843 (1998-04-01), Efland et al.
patent: 5777383 (1998-07-01), Stager et al.
patent: 5859456 (1999-01-01), Efland et al.
patent: 5900764 (1999-05-01), Imam et al.
patent: 5910669 (1999-06-01), Chang et al.
patent: 5946202 (1999-08-01), Balogh
patent: 5969513 (1999-10-01), Clark
patent: 5973367 (1999-10-01), Williams
patent: 6020729 (2000-02-01), Stratakos et al.
patent: 6023155 (2000-02-01), Kalinsky et al.
patent: 6031361 (2000-02-01), Burstein et al.
patent: 6097064 (2000-08-01), Saitoh et al.
patent: 6100583 (2000-08-01), Ohmori
patent: 6100676 (2000-08-01), Burstein et al.
patent: 6114726 (2000-09-01), Barkhordarian
patent: 6150150 (2000-11-01), Livi et al.
patent: 6150722 (2000-11-01), Efland et al.
patent: 6160441 (2000-12-01), Stratakos et al.
patent: 6198261 (2001-03-01), Schultz et al.
patent: 6225795 (2001-05-01), Stratakos et al.
patent: 6268716 (2001-07-01), Burstein et al.
patent: 6271651 (2001-08-01), Stratakos et al.
patent: 6278264 (2001-08-01), Burstein et al.
patent: 6288919 (2001-09-01), Jain
patent: 6329801 (2001-12-01), Zuniga et al.
patent: 6351108 (2002-02-01), Burstein et al.
patent: 6404173 (2002-06-01), Telefus
patent: 6421262 (2002-07-01), Saxelby et al.
patent: 6462521 (2002-10-01), Yang et al.
patent: 6462522 (2002-10-01), Burstein et al.
patent: 6476442 (2002-11-01), Williams et al.
patent: 6476443 (2002-11-01), Kinzer
patent: 2001/0035746 (2001-11-01), Burnstein et al.
patent: 2001/0038277 (2001-11-01), Burnstein et al.
patent: 2002/0104872 (2002-08-01), DeFelice et al.
patent: 406260927 (1994-09-01), None
Design of Pulse Width Modulation Based Smart Switch Controller for Automotive Application; Athalye et al.; 10/99; pp. 8.C.1-1-1-7.
“Analysis and Implementation of a Semi-integrated Buck Converter with Static Feedback Control”; Strandberg et al.; Jun. 29, 1999; 4 pp.
“Role of Semiconductor Devices in Portable Electronics Power Management”; Mohamed Darwish; Aug. 9, 2000; 4 pp.
“Motorola to Preview Next-generation Smart Power Technology at World's Leading Power Conference”; http://www.apspg.com/procs/060100/smart.html; Jun. 29, 2001; 2 pp.
“IEAI204T: High Efficiency DC/DC Converter”; http://www.semiconductors.philips.com/pip/teal204t.html; Jun. 29, 2001: 3 pp.
“Synchronous Rectification with Adaptive Timing Control”; Ackes et al.: 06/95: pp. 88-95.
“High-Efficiency Low-Voltage DC-DC Conversion for Portable Applications”; Stratakos; The 12th International Symposium on Power Semiconductor Devices & ICs; 1998; pp. 1-245.
“A Low Voltage CMOS Compatible Power MOSFET for On-Chip Dynamic Voltage Scaling DC-DC Converters” Nassif-Khalil et al.; Jan. 2000; pp. 43-46.
“FlipFET™ MOSFET Design for High Volume SMT Assembly”; Schofield et al. ; http://www.isf.com/technical-info/papers.html; Mar. 18, 2001; 6 pp.
“Active Clamp Circuits for Switchmode Regulators Supplying Microprocessor Ioada” Sauders et al.; May 1997; pp. 1179-1185.
“An Active Clamp Circuit for Voltage Regulation Module (VRM) Applications”; Wu et al.; IEEE Transactions on Power Electronics, vol. 16, No. 5; Sep. 2001; pp. 623-634.
“An Integrated Controller for a High Frequency Buck Converter”; Lau et al.; May 1997; pp. 246-254.
“A Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System”; Stratakos et al; May 1994; pp. 619-626.
“International Rectifier Introduc
Eden Richard C.
Smetana Bruce A.
Isothermal Research Systems, Inc.
Ngo Ngan V.
Wells St. John P.S.
LandOfFree
POWER SEMICONDUCTOR SWITCHING DEVICES, POWER CONVERTERS,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with POWER SEMICONDUCTOR SWITCHING DEVICES, POWER CONVERTERS,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and POWER SEMICONDUCTOR SWITCHING DEVICES, POWER CONVERTERS,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3187745