Power semiconductor packaging method and structure

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step

Reexamination Certificate

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C257S727000

Reexamination Certificate

active

07829386

ABSTRACT:
A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

REFERENCES:
patent: 4835704 (1989-05-01), Eichelberger et al.
patent: 5151769 (1992-09-01), Immorlica, Jr. et al.
patent: 5169678 (1992-12-01), Cole et al.
patent: 5258647 (1993-11-01), Wojnarowski et al.
patent: 5324687 (1994-06-01), Wojnarowski
patent: 5355019 (1994-10-01), Fuchs
patent: 5449427 (1995-09-01), Wojnarowski et al.
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5532512 (1996-07-01), Fillion et al.
patent: 5554305 (1996-09-01), Wojnarowski et al.
patent: 5576517 (1996-11-01), Wojnarowski et al.
patent: 5637922 (1997-06-01), Fillion et al.
patent: 5672546 (1997-09-01), Wojnarowski
patent: 5785787 (1998-07-01), Wojnarowski et al.
patent: 5949133 (1999-09-01), Wojnarowski
patent: 6002162 (1999-12-01), Takahashi et al.
patent: 6229203 (2001-05-01), Wojnarowski
patent: 6297459 (2001-10-01), Wojnarowski et al.
patent: 6306680 (2001-10-01), Fillion et al.
patent: 6410356 (2002-06-01), Wojnarowski et al.
patent: 2002/0121691 (2002-09-01), Wojnarowski et al.
patent: 0452506 (1991-10-01), None
patent: 0465197 (1992-01-01), None
patent: 0559384 (1993-09-01), None
patent: 0896367 (1999-02-01), None
patent: 0021027 (2000-04-01), None
EP Search Report, EP06254260, Sep. 3, 2007.
A. Welling et al., Fast implementation of the single scatter simulation algorithm and its use in interactive image reconstruction of PET data,: Institute of Physics Publishing, Phys. Med. Biol. 47 (2002), pp. 2247-2960.
M. Popall et al., “Ormocer®s—Inorganic-Organic Hybrid materials for e/o—interconnection-Technology,” Mil. Cryst. and Liq. Cryst, 2000, vol. 354, pp. 123-142.
Fraunhofer Institut Silicatforschung Annual report 2003, Ormocers, pp. 44-48.
Letter Providing English summary of Dec. 7, 2009 Israeli Office Action of Israeli Patent Application No. 177322.
CPEL0654196, First Office Action, Patent Application No. 200610115024.7, Aug. 28, 2009.
Application No. 06254260.0, EP Office Action, May 29, 2008.

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